Canon A-200 series Service Manual page 98

• V-RAM Read Timing
1. When the CPU emits the MRD signal, the 1/0 READY signal becomes disabled and the
CPU then becomes the wait state.
2. The pin 8 of U1 becomes HIGH at the falling edge of the
S/L
signal, and is reset at the rising
edge of the next CRTC-CLK signal. When the signal from the pin 8 of U1 is HIGH and when
this signal is accessing the V-RAM in the CPU cycle, the OE signal of the 6116 then becomes
LOW.
3. Next, a data is output from the 6116. This data is latched at the rising edge of the 1/0 READY
signal and simultaneously, it makes the 1/0 READY signal enable.
4. The CPU then reads the data which has been latched at the falling edge of the T4 cycle.
5. When the CPU enters into T4 cycle, the MRD signal becomes HIGH and an impedance of
110 READY signal keeps high.
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