Vi-2-8. Dmac - Canon A-200 series Service Manual

VI-2-8. DMAC
The DMAC performs two important operations. One is a data transfer between memory and
1/0 devices and the other is refreshment for D-RAMs. However, the relationship between
these two operations and the CPU is basically identical.
Figure 6-13 shows a concept for the DMA operation.
As for the A-200, the DMA operation is performed in the cycle steal mode and so, an insertion
of the wait cycle is done by using the READY signal.
The DREO signal from the 1/0 notifies the DMAC of a DMA request. Then the DMAC also notifies
the CPU of that DMA request by making the HRO signal lOW.
For the DMAC to judge whether an instruction cycle has been completed or not, this HRO signal
becomes to the DMAGO signal at U79 by being ANDed with 80, 81, 82 and lOCK signals.
This DMAGO signal is latched by U109 at the falling edge of the ClK signal and becomes the
HOLDA signal.
The HOLDA signal tells the DMAC that the CPU will insert TW signal between T3 and T4.
While, a signal delayed for a half clock cycle at U108 becomes the AEN signal, and an inverted
signal of it - AEN is sent to the CEN terminal of the BCU and finally, it makes the BCU inactive.
The AEN signal is then delayed for one clock cycle at U108 and becomes lOW level RDY signal.
This signal makes the READY terminal of the CPU to lOW. The CPU keeps inserting TW signal
between T3 and T4 during lOW level of that terminal.
The DMAC performs data transferring between the 1/0 and memory while the CPU keeps insert ­
ing TW signals.
In addition, since an address control of the DMAC requires 16-bit bus, U78 makes up for want
of 4 bits.
Figure 6-14 and 6-15 show the timing chart for the DMA operation and one for refreshment for
D-RAMs respectively.
LOCK
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HOLDA
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AEN17
Figure 6-13
63