Canon A-200 series Service Manual page 72

UART has the following significant features:
*
Full double buffering eliminates need for precise synchronization.
* Independently controlled transmit, receive, line status, and data set interrupts.
*
Programmable baud generator allows division of any input clock by 1 to (2
16
_1) and gener ­
ates the internal 16 x clock.
* Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from
serial data stream.
*
Line break generation and detection.
*
Internal diagnostic capabilities:
- Loopback controls for communications link fault isolation.
- Break, parity, overrun, framing error simulation.
* Full prioritized interrupt system controls.
*
MODEM control functions (CTS, RTS, DSR, DTR, RI and DCD).
* Fully programmable serial-interface characteristics:
- 5; 6; 7; or 8-bit characters
- Even, odd, or no-parity bit generation and detection.
- 1; 1-1/2; or 2-stop bit generation
- Baud generation (DC to 56k baud).
* False start bit detection.
* Complete status reporting capabilities.
When the CPU assigns one of addresses 3F8 through 3FFH as I/O address, the LOW level UART
signal from the I/O address decoding circuit is sent to the UART. The UART then selects the inter­
nal register to be connected to the data bus according to the status of AD through A2 terminal
and RD and WR terminal, and the status of DLAB (Divisor Latch Access Bit).
-DLAB is bit7 of the line control register.
Table 6-6 shows the status of registers indicated by each I/O address.
I/O Address A2 A1
AD
RD WR DLAB
3F8
L L L L H X Receive Buffer
3F8
L L L H L X Transmit Buffer
3F8 L L L * *
1
Divisor Latch LSB
3F9
L L H * * 1 Divisor Latch MSB
3F9 L
L H * *
D
Interrupt Enable Register
3FA L H L * * X Interrupt Identification
Register
3FB L H H * * X Line Control Register
3FC H L
L * * X MODEM Control Register
3FD
H L H * * X Line Status Register
3FE H H
L
* *
X
MODEM Status Register
*.
RD becomes LOW when read operation.
WR becomes LOW when write operation.
X: Don't care.
Table 6-6
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