Vi-2-2. Reset Signal And Clock Generator Circuit - Canon A-200 series Service Manual

• LOCK (Lock) ..... output in three states
The lOCK signal denotes that the CPU cannot be controlled by the system bus during another
system bus master or lOCK signal is active (lOW). This signal becomes active with the preposi­
tioned "lOCK" instruction and remains active until the execution of the next one instruction has
been completed. This signal's impedance keeps high during local bus's hold acknowledgement.
• QS1, QSO (Queue Status) ..... outputs
These signals output the status of the instruction queue to the 8087 NDC.
QS1 QSO
o
o
No operation (queue is not changed)
o
1 Indicates that the queue is the first byte of the ope-code.
o
Indicates that the queue register is empty.
Indicates that the queue is the second or upper byte of the in­
struction.
These signals are effective during next clock cycle of when the queue operation has been executed.
• S2, S1, SO (Status) ..... outputs in three states
These status signals are encoded as follows
S2 S1 SO
0 0 0
Interrupt acknowledge
0 0 Read I/O ports
0 0 Write I/O ports
0 1 1 Halt
1 0 0 Code access
1 .
0
1
Read memory
1 0 Write memory
1 Passive
These status signals become active during the period of T4, T1 and T2, and return to passive
(111) condition during TW.
These signals are used by the BCU to generate all the memory and I/O signals. A change of
S2, S1 and SO at the period of T4 is used to indicate the beginning of the bus cycle, and a pas­
sive state of the bus at T3 or TW is used to indicate the end of the bus cycle.
These signal's impedance will remain high during hold acknowledge cycle of the local bus.
• RQ/GTO,
TEST
These terminals are not used and therefore are pulled up to the power supply line 0Jcc).
• RQ/GT1
This terminal is connected to the RQ/GTO terminal of the NDC for the purpose of multi-bus operation.
VI-2-2. RESET Signal and Clock Generator Circuit
Figure 6-4 shows the RESET signal and ciock generator circuit. The lSI 8284 is the heart of
this circuit. It generates RESET, elK, PClK, READY and OSC signals.
The RESET signal is generated by detecting a rising up of Vcc connected to the RES terminal,
and is sent to the CPU, each device and option slots. This signal is also generated by pushing
the RESET switch located on the front panel.
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