Vi-3. Keyboard Unit - Canon A-200 series Service Manual

VI-3. Keyboard Unit
Figure 6-26 is a block diagram for the keyboard unit.
This unit employs 8048 (or 8784) 8-bit one chip microprocessor and is not synchronized with
the main PCB.
The 8048 (or 8784) has 64-byte RAM and 1K-byte ROM. The RAM is used as the key buffer
and the ROM contains the control programs including the self-diagnostics.
Signal P10 through P17 and P20 through P22 in the figure are used as key scan signals,· and
DBO through DB7 is used as key return signals.
Interface between the main PCB is done at P23, P27, TO and T1 terminals. P23 transmits a key
clock signal, P27 also transmits a key data.
The CPU checks the TO terminal to judge whether a key clock signal is output or not. This is
to detect "soft reset" status that the keyboard interface on the main PCB shows by making the
key clock signal line to LOW level for 20 milli seconds.
Similarly, the T1 terminal is used for the CPU to judge whether the buffer in the keyboard inter­
face on the main PCB is full or not.
When the buffer in the keyboard interface is full, the keyboard interface will force the key data
signal line to make LOW level.
The CPU sends the key scan signals to the key matrix and judges conditions for every key by
reading the key return signals.
If anyone of the keys is pressed, the CPU emits a key code signal corresponding to that key
and sends it to the main PCB together with a key clock signal sequentially.
At this time, the CPU sends 7-bit key code and also 1-bit condition code which tell the condition
of every keys.
When a key is changing from OFF to ON, the bit is LOW and changing from ON to OFF, HIGH.
Table 6-11 is key code table.
Figure 6·26
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