Vi-2-11. Timer And Speaker Driver Circuit - Canon A-200 series Service Manual

VI-2-11. Timer and Speaker Driver Circuit
Figure 6-19 shows the timer and speaker driver circuit.
Mainly, this circuit has the following functional features.
* Generates an interruption signal when the predetermined timer becomes active.
*
Requests the DMAC to refresh D-RAMs at every 15 micro seconds.
* Determines frequency of a signal to be sent to the speaker.
Above operations are performed based on a clock signal which is obtained by dividing the fre­
quency of the PCLK signal (2.39MHz) from the CG into a half at U107.
The PIT has three sets of 16-bit counter, and they have independent output terminals QUTO, QUT1
and QUT2 respectively.
The QUTO terminal sends an interruption signal to the CPU through the PIC when the predeter ­
mined timer counting has been completed.
The QUT1 terminal outputs a refresh request signal to the DMAC at every 15 micro seconds.
This signal is latched by U87 and is reset by an acknowledgement signal (DACKO) sent from
the DMAC.
The QUT2 terminal generates an audio frequency signal for the speaker according to require­
ments of the software. This signal is NANDed with the PB1 signal sent from the PPI and then
drives the transistor 03 to sound the speaker.
Table 6-7 shows data loadings and reading for every counter.
PIT
PIC
IRO
Vee
DO
I
DREOO
au
DACKO
PBO
> - - - - - - - - 1
G2 aUT2 PC5
Vee
RD
IOW-N
r - - - - - - - Q
WR
CN12
PIT > - - - - - - - - 1 CS
(]
AO or BAO > - - - - - - - - 1 AO
PBl
A l o r B A 1 > - - - - - - - - I A
QI-+--.--IC lK
ClK
PClK ClK
Figure 6-19
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