Vi-2-6. 110 Map And 1/0 Address Decoding Circuit - Canon A-200 series Service Manual

VI-2-6. I/O Map and I/O Address Decoding Circuit
Figure 6-11 shows the 1/0 address decoding circuit. This circuit generates the chip enable sig ­
nals for LSls and registers mounted on the main p.e.B.
The decoder U51 generates the chip enable signal for the 1/0 devices existing on the 110 ad ­
dresses 000 to OFF, and U117 generates the chip enable signal for the 110 devices existing
on the 1/0 addresses 360
to 3FF.
Table 6-2 shows the schema of 1/0 map.
....
-....-­
A2
.-
113
~
FOC
,--J
1 27
-
.....
.-
G1
Y7 f:>
I~
Y6f:>
.....
A9
, Ul17
Y5 f:>
.....
A8
"...
1,;\
G28
Y4p
A6 .-
~.
G2A Y3
UART
~
.....
A5
'--- C
Y2
p-­
.....
A7 ,,- 8 Y1
.....
A3
.-
A YO
P
107
"...
D Q NMIEN
87
....
IOW-N
-- ­
NMIC C
;J
84
R
-
RESET]
-...---
Gl Y7
P
:=d -
84
f
U51
Y6 f:>
Y5
p­
-
" G2B
Y4
G2A
-
Y3
PPI
C
-
Y2
PIT
-
B
Yl PIC
-
A YO
OMAC
Figure 6-11
57