Canon A-200 series Service Manual page 107

CPu/CRTC
This clock is selected by the HRES signal. Namely, when the screen is in 40
x
25 pixels text
mode, an output signal of U65-2 pin is used as the CPUtCRTC signal, and when 80
x
25 pixels
mode, an output of U39-6 pin is used.
CRT-ClK
This clock signal is also selected by the HRES signal. When the screen is in 40 x 25 pixels
text mode, an output signal of U66-2 pin is used as the CRT-ClK signal and when 80
x
25
pixels mode, an inverted signal of U65-7 pin output is used.
The CRT-ClK controls the fundamental operations of the CRTC.
DOT-ClK
This signal is also selected by the HRES signal. When the screen is in 40 x 25 pixels text mode,
an output signal of U65-10 pin is used as the DOT-ClK signal, and when 80 x 25 pixels mode,
an inverted signal of the OSC signal (14.31818MHz).
This DOT-ClK signal is used as the timing clock for shifting the dot data in the character mode,
or when the graphics mode, this signal is used as the latch clock of every bit.
siC
This signal is selected by the HRES signal. When the screen is in 320 x 200 pixels of graphics
mode, an Ex-ORed signal of U66-2 pin output and U65-5 pin output, and an NORed signal of
U18-2 pin output and U66-5 pin output are ORed at U58, and this signal is used as the
SIC
sig­
nal. For 640 x 200 pixels screen, the cycle of the S/L signal is extended to a double, and used
as the lOAD signal of the shift register which shifts the dot data in the graphics mode.
CAS
This signal is an ANDed signal of U64-2 pin output and U60-6 pin output. This clock is used
for the V-RAM.
RAS
This signal is an Ex-ORed signal of U66-2 pin and U65-2 pin.
Further, the RAS signal is ANDed with the V-RAM decode signal and used as the RAS signal
of the V-RAM.
* Clock Timing
80 x 25 or 40 x 25 Characters Text Mode
The address signal from the CRTC is output at the falling edge of the CRT-ClK clock signal.
This address is latched at the rising edge of the RAS signal and then is divided into the row
address and column address by the CRTC-RAS ADDR and CRTC-CAS ADDR signals. The row
address is read at the falling edge of the RAS signal and the column address is read at the falling
edge of the CAS signal. At the same time, data is output from the D-RAM. This data is latched
at the falling edge of the CH-lATCH and the AT-lATCH signals.
Output signals of the U27 are used as the address signals of the character generator (2364)
and outputs from the U28 are used as the attribute signals.
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