Canon A-200 series Service Manual page 52

• SHE/S7 (Sus High Enable/Status) ..... output in three states
During T1, the SHE signal is used to permit the upper half of the data bus (015 - 08) to output
data. An 8-bit type device connected to the upper half of the bus uses the BHE signal for chip
selecting purpose.
When one byte is sent at the upper half of the bus, BHE becomes lOW during read, write and
interrupt acknowledge cycle.
S? status information will yield during the period of T2, T3 and T4. The BHE signal is active lOW
and its impedance is high during hold acknowledge cycle of the local bus. This signal becomes
lOW during T1 of the interrupt acknowledge cycle.
• RD (Read Strobe) ..... output in three states
This signal indicates that the CPU is now executing memory read (S2=1) or I/O read (S2=0) cy­
cle. The RO signal is used to read devices which are connected on the 8086 local bus line.
This RO signal keeps active lOW during memory read cycle T2, T3 and TW. At T2,until the 8086
local bus's impedance becomes high, the RO remains HIGH.
This signal becomes high impedance during the hold acknowledge cycle of the local bus.
• READY (Ready) ..... input
This acknowledgement signal denotes that the data transfer has been completed, and are sent
from memory or I/O devices which CPU has been addressed.
The ROY signal from memory or I/O devices will become the READY signal synchronized with
the ClK signal by the CG.
• INTR (Interrupt Request) ..... input
This signal is a trigger input sampled between the last clock cycle of each instruction in order
for the CPU to determine whether the interrupt acknowledge operation is performed or not.
One subroutine is assigned through one interrupt vector lookup table which is located on the
system memory.
The INTR signal can be internally masked by resetting the interrupt enable flag (IF) with the soft ­
ware. This signal is active HIGH.
• NMI (Non Maskable Interrupt) ..... input
The NMI signal is an edge trigger input which causes the type-2 interrupt. One subroutine is
assigned through one interrupt vector lookup table which is located on the system memory.
This signal cannot be masked by the software. If there is a raising edge from lOW to HIGH,
an interruption will occur after an instruction curretly executing is completed.
As for the A-200, a memory parity error gated with the NMIEN signal and the interrupt signal
for the NOC are input to the CPU.
• RESET (Reset) ... _. input
This signal terminates the operation of the CPU immediately. The RESET signal must be kept
HIGH for at least four clock cycles. When the RESET signal returns to lOW, the CPU outputs
the first address (FFFFOH) and then restarts executing after 10 clock cycles has been passed.
• ClK (ClOCk) ..... input
This clock supplies the fundamental timing signal to the CPU. In order to obtain optimum internal
timing, the ClK must be an asymmetric wave with 33% of duty cycle.
This clock signal is obtained by dividing the 14.31818MHz fundamental clock by three with the
8284 clock generator.
• MN/MX ..... input
This terminal determines whether the 8086 is operated in minimum mode or maximum mode.
In this computer, the CPU is operated in maximum mode and to achieve this, this terminal is
connected to the ground.
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