Canon A-200 series Service Manual page 54

The diode MA150 is used to discharge the 47-micro-farad capacitor.
The ClK signal is obtained by dividing by three the fundamental clock, generated by the
14.31818MHz quartz crystal connected to this IC. This signal is sent to the CPU and constructed
the duty ratio as shown in Figure 6-5.
The PClK signal is made by dividing the ClK signal into the half and used as the clock input
for the timer circuit or the timing clock for the keyboard interface.
The OSC signal is 14.31818MHz clock and sent to the monochrome board or color board through
the option slots.
The READY signal indicates that one instruction cycle of the CPU has been completed. This sig­
nal is made from the AEN1 and RDY1 signals. The READY signal is cleared after the guaranteed
hold time to the CPU has been met.
DClK is made from the OSC and ClK signals and used as a clock signal for the 8237 (DMAC).
Vee
C.G (8284)
, . . . . - - - - - - - - R E S E T
10K
>--------~D
, . . . - - - - - - R E S E T
C
>------RESET
(To optional slot)
:>O---f------{}--'Vv\..-.....--------osc
f - - - - < > - - - - - + - - - - - - - - P C l K
, . . . - - - - - - - C L K
>-----<J~tv_+~t--+-__175
ClK
(To optional slots)
C
D Qt--"'--"
DClK
RDY1>---~>---___r~
U131
D 0 f----<)--'
C
AENT>----O--I
' - - - - - - - - - - - R E A D y
Figure 6-4
OSC
CLK.-J
PCLK---.....
L
Figure 6-5
51