Pll Circuits - Icom IC-F310 Service Manual

4-2-3 DRIVE AMPLIFIER CIRCUIT (MAIN unit)
The drive amplifier circuit amplifies the VCO oscillating sig-
nal to the level needed at the power amplifier.
The RF signal from the buffer amplifier (Q4) passes through
the T/R switch (D5) and is amplified at the buffer (Q3, Q2)
and drive (Q1) amplifiers. The amplified signal is applied to
the power amplifier circuit.
4-2-4 POWER AMPLIFIER CIRCUIT (MAIN unit)
The power amplifier circuit amplifies the driver signal to an
output power level.
The RF signal from the drive amplifier (Q1) is applied to the
power module (IC1) to obtain 45 W (for IC-F320; 25 W for
IC-F310) of RF power.
The amplified signal is passed through the antenna switch-
ing circuit (D3, D4), low-pass filter and APC detector, and is
then applied to the antenna connector.
Collector voltages for the driver (Q1) and control voltage for
the power amplifier (IC1, pin 2) come from APC controller
(Q17, Q18) to stabilize the output power. The transmit mute
switch (Q23) controls the APC controller when transmit mute
is necessary.
4-2-5 APC CIRCUIT (MAIN unit)
The APC circuit protects the power amplifier from a mis-
matched output load and stabilize the output power.
The APC detector circuit (D1, D2) detects forward signals
and reflection signals at D2 and D1 respectively. The com-
bined voltage is at minimum level when the antenna imped-
ance is matched at 50 Ω and is increased when it is mis-
matched.
• PLL circuit
30.6 MHz signal
to the FM IF IC
VCO circuit
Q7, Q8
D7, D8
Loop
filter
IC2 (PLL IC)
Phase
8
detector
Programmable
17
×2
divider
15
The detected voltage is applied to the inverse amplifier
(IC6c, pin 9), and the power setting voltage (T4) is applied
to the other input (pin 10) for the reference. When antenna
impedance is mismatched, the detected voltage exceeds
the power setting voltage. The output voltage of the inverse
amplifier (IC6c, pin 8) controls the input current of the power
module (IC1) and drive amplifier (Q1) to reduce the output
power via the APC controller (Q17, Q18).

4-3 PLL CIRCUITS

4-3-1 PLL CIRCUIT
A PLL circuit provides stable oscillation of the transmit fre-
quency and receive 1st LO frequency. The PLL circuit con-
sists of the PLL IC (IC2), loop filter and reference oscillator
circuit and employs a pulse swallow counter.
An oscillated signal from the VCO (Q7, Q8) passes thorough
the buffer amplifiers (Q6, Q5) is applied to the PLL IC (IC2,
pin 2) and is prescaled in the PLL IC based on the divided
ratio (N-data). The reference signal is generated at the ref-
erence oscillator (X1) and is also applied to the PLL IC. The
PLL IC detects the out-of-step phase using the reference
frequency and outputs it from pin 8. The output signal is
passed thorough the loop filter (R43–R45, C60, C61) and is
then applied to the VCO circuit as the lock voltage.
4-3-2 VCO CIRCUIT (MAIN unit)
The VCO oscillated signal is amplified at the buffer ampli-
fiers (Q6, Q4) and is then applied to the T/R switching circuit
(D5, D6). The Rx signal is applied to the 1st mixer circuit
(Q13) via the bandpass filter (L23, L24, C116–C118) and the
Tx signal to the driver (Q1) via the buffer amplifers (Q2, Q3).
A portion of the signal from Q6 is amplified at the buffer
amplifier (Q5) and is then fed back to the PLL IC (IC2 pin 2).
Buffer
Q4
Buffer
Q6
Buffer
Q5
Programmable
Prescaler
counter
Shift register
X1
15.3 MHz
4 - 3
D5
to transmitter circuit
to 1st mixer circuit
D6
2
3
PLST
4
SCK
5
SO