Operational States Of An Interrupt Level - Xerox 560 Reference Manual

Interrupt
State FF Configuration
Disarmed
~
i"
Armed
[$
III'
Waiting
[$
I
Active
~
Level
Enable
Source of
Change Signal
Basic Processor
Basic Processor
or External Signal
~
I
I---
Bas i c Processor
Interrupt Timing
Group Inhibit off
No higher-priority level active,
or waiting and enabled
Figure 10. Operational States of an Interrupt Level
When an interrupt level is in the waiting state, the follow-
ing conditions must all exist simultaneously before the level
advances to the active state:
1.
The level must be enabled (i .e., its enable/disable
fl ip-flop must be set to one).
2.
The group inhibit (CI,
II, or El, if applicable) must be
zero.
3.
No higher-priority interrupt level is in the active
state, or is in the waiting state, enabled, and not
inhibited.
4.
The basic processor must be at an interruptible point
in the execution of a program.
Note that one or more interrupt levels of higher priority can
also be in the waiting state if they are disabled, inhibited,
or both disabled and inhibited.
Generally, if the enable/disable flip-flop is off (level is
disabled), the interrupt level can undergo all state changes
except that of moving from the waiting to the active state
(see exception case, below). Furthermore, if the interrupt
level is disabled, it is completely removed from the chain
that determines the priority of access to the basic processor.
Thus a disabled interrupt level in the waiting state does not
prevent an enabled, waiting interrupt level of lower priority
from moving to the active state.
Note this exception to the foregoing description: Although
generally no interrupt level can move from the waiting state
to the active state unless it is enabled, a specia
I
form of the
WD instruction can move a waiting level to the active state
whether or not the level is enabled.
ACTIVE
After the basic processor has successfully accessed the in-
terrupt instruction, then the interrupting level advances to
the active state. When all the conditions for acknowledg-
ment have been achieved, the interrupt level causes the
Central ized Interrupts 31