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2. HARDWARE CONFIGURATION GUIDELINES
INTRODUCTION
This chapter is intended as an aid to the system manager in
selecting the proper hardware for his RBM system.
A
reasonable selection of hardware can be made only on the
basis of a thorough understanding of the particular applica-
tion's requirements.
Requirements that must be evaluated
include the number of discrete interrupt leve Is required,
the amount of secondary storage required for programs and
data, memory requirements to satisfy resident foreground
needs and concurrent batch (if desired), and peripheral
equipment requirements for the data media desired. Figure
illustrates the lowest-cost minimum RBM configuration.
Figure 2 illustrates a more typical RBM configuration.
HARDWARE INTERRUPT REQUIREMENTS
The maximum number of foreground tasks that are expected
to operate concurrently determines the number of hardware-
interrupt levels required, in addition to those needed by
RBM itself.
The association of an interrupt level with a
task establishes the priority of the task.
The task's worst-
case response time (to an external stimulus) is dependent
upon the maximum RBM inhibit time and the possible activity
of higher priority tasks.
Tasks that are prioritized above
Core Memory (8K)
Memory Protect
Power Fai I Safe
Xerox
Extended Arithmetic
530
CPU
Multiply;'bivide
4101
Integral Interrupts (6)
Real-Time Clocks (2)
lOP with 16 channels
Keyboard Printer Control
~
~
r:
Remote
(KSR-33)
Assistance
Interface
the I/O interrupt task must contend only with the RBM
maximum inhibit of
100~ec
and possible interference among
themse I ves.
The standard Xerox 530 is equipped with two interrupt levels,
Integral 5 and Integral 6, thatare higher in priority than the
I/o interrupt task. (Sigma 2/3 can have a larger number of
these. ) Tasks associated with an interrupt priority higher than
I/O cannot utilize any RBM services that involve I/o; thus
these higher interrupt levels are typically associated with
high priority tasks that uti I ize the Direct I/o interface with
SIUs and defer RBMservices to related, lower-priority tasks.
Tasks that operate at a priority lower than the I/O interrupt
level can utilize all RBM services including I/O. Any num-
ber of these tasks may operate concurrently up to the number
of available lower-priority hardware inter:rupts minus one.
(The RBM Control Task requires the lowest-priority hardware
interrupt level actually uti I ized in the system.) For tasks
below the I/O level, the I/o interrupt can cause an inter-
ference of up to approximately 500 microseconds, however
since I/O interrupts can stack up, the interference can be
extended in order to service all pending interrupts.
The same hardware interrupt can be used "serially" by
different tasks, but on Iy one can be connected to a given
interrupt at anyone time. Table 1 gives a comparison of
the Sigma 3 and 530 interrupt structures.
4151
Core Memory
(8K)
f""'"
~
'-
..,..
7250
7251
Disk Controller
(2.3 mb)
-"
Binary
Input
Device
Figure
1.
RBM Lowest-Cost, Minimum Configuration
Hardware Configuration Guidelines
3
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