Floating-Point Arithmetic Fault Trap; Decimal Arithmetic Fault Trap - Xerox 560 Reference Manual

Hide thumbs Also See for 560:
Table of Contents

Advertisement

2.
CC1 t
CC2 CC3 CC4 Meaning
o
No carry out of bit 0 of the
adder (add and subtract in-
structions only).
Carry out of bit 0 of the
adder (add and subtract in-
structions only).
If the instructi on trapped was a DW or DH, the stored
condition code is interpreted as follows:
CC1
CC2 CC3 CC4 Meaning
tt
Overflow
Load the new PSWs. The condition code and instruc-
tion address portions of the PSWs remain at the value
loaded from memory.
FLOATING-POINT ARITHMETIC FAULT TRAP
Floating-point fault detection is performed after the opera-
tion called for by the instruction code is performed, but
before any results are loaded into the general registers.
Thus, a floating-point operation that causes an arithmetic
fault is not carried to completion in that the original con-
tents of the genera I reg isters are unchanged.
Instead, the basic processor traps to location X ' 44
1
with the
current condition code indicating the reason for the trap.
A characteristic overflow or an attempt to divide by zero
always results in a trap condition. A significance check or
a characteristic underflow results in a trap condition only
if the floating-point mode controls (FS, FZ, and FN) in the
current program status words are set to the appropriate state.
If a floating-point instruction traps, the execution of XPSD
or PSS in trap location X ' 44
1
is as follows:
1.
Store the current PSWs.
(Store general registers if
P~~.)
If division is attempted with a zero divisor or
if characteristic overflow occurs, the stored condition
code is interpreted as follows:
CCl
CC2 CC3 CC4 Meaning
o
o
o
o
o
o
o
Zero divisor.
Characteristic overflow,
nega t i ve resu I
t.
Characteristic overflow,
positive result.
tCCl remains unchanged for instructions LCW, LAW, LCD,
and LAD.
ttA hyphen indicates that the condition code bits are not af-
fected by the condition given under the "Meaning
ll
heading.
42
Trap System
If none of the above conditions occurred but charac-
teristic underflow occurs with floating zero mode
bit (FZ)
=
1, the stored condition code is interpreted
as follows:
CCl
CC2 CC3 CC4 Meaning
o
o
Characteristic underflow,
negative result.
Characteristic underflow,
positive result.
If
none of the above conditions occurred but an addi-
tion or subtraction results in either a zero result (with
FS
=
1 and FN
=
0), or a postnormal ization shift of
more than two hexadecimal places (with FS
=
1 and
FN
=
0), the stored condition code is interpreted as
follows:
CC1
CC2 CC3 CC4 Meaning
0
0
0
Zero result of addition or
subtraction.
0
0
More than two postnormaliz-
ing shifts, negative result.
0
0
More than two postnormaliz-
ing shifts, positive result.
2.
Load the new PSWs. The condition code aild instruc-
tion address portions of the PSWs remain at the values
loaded from memory.
DECIMAL ARITHMETIC FAULT TRAP
When either of two decimal fault conditions occurs (see
Chapter 3, IIDecimal Instructions
ll
) ,
the normal sequencing
of instruction is halted, CCl and CC2 are set according to
the reason for the fault condition, and CC3, CC4, memory,
and the decimal acclJrnulator remain unchanged
by
the in-
struction.
If
the decimal arithmetic trap mask (bit posi-
tion 10 of PSW1) is a 0, the instruction execution sequence
continues with the next instruction in sequence at the time
of fault detection; however, if the decimal arithmetic trap
mask contains a 1, the basic processortrapstolocationX ' 45
1
at the time of fault detection. The following are the fault
conditions for decimal instructions:
Instruction Name
Mnemonic
Fault
Dec i rna I Load
DL
I II ega I dig i t
Decimal Store
DS
Illegal digit
Decimal Add
DA
Overflow, i lIega I
digit
Decimal Subtract
DS
Overflow, illegal
digit
Decimal Multiply
DM
Illegal digit

Advertisement

Table of Contents
loading

Table of Contents