Execute/Branch Instructions; Nonallowed Operation Trap During Execution Of Branch Instruction - Xerox 560 Reference Manual

Note; If the word count
~
28, the effective doubleword
(ED) is pulled from memory stack locations (rela-
tive addresses initial TSA-24 and initial TSA+l).
If the word count=O, the ED is pulled from real
memory locations 2 and 3.
Status Stack Pointer Doubleword; (Only if initial Word
Count
~
28)
TSA-1 --TSA until terminal TSA = initial TSA-28;
Word Count - 1 - - Word Count unti
I
terminal Word
Count
=
initial Word Count - 28 (if initial Word Count
>
32,767, bit 48 not affected); and,
Space Count + 1 - Space Count untir terminal Space
Count = initial Space Count + 28 (if Space Count
>
32,767, then set bit 32 to 1).
Interrupt System;
. If
(1)10
=
1 and (1)11
=
1, clear and arm interrupt
level.
If
(1)10
= 1 and (1)11
=
0, clear and disarm interrupt
level.
EXECUTE/BRANCHINSTRUCT~NS
The following instructions can cause the basic processor to
execute instructions in an order other than that of sequen-
tially ascending instruction addresses:
Instruction Name Mnemonic
Execute
EXU
Branch on Conditions Set
BCS
Branch on Conditions Reset BCR
Branch on Incrementing Register BIR
Branch on Decrementing Register BDR
Branch and Link BAL
The EXECUTE instruction can be used to insert another in-
struction into the program sequence, and the branch in-
structions can be used to alter the program sequence, either
unconditionally or conditionally. If a branch is uncondi-
tiona! (or conditional and the branch condHion is satisfied),
the instruction pointed to by the effective address of the
branch instruction is normally the next instruction to be
executed. If a branch is conditional and the condition
for the branch is not satisfied, the next instruction is nor-
mally taken from the next location, in ascending sequence,
after the branch instruction.
106 Execute/Branch Instructions
NONALLOWED OPERATION TRAP DURING EXECUTION
OF BRANCH -INSTRUCTION
The next instruction after a branch instruction may reside
in two possible places: the location following the branch
instruction or a location designated by the branch instruc-
tion. Either of these two locations may be in a protected
memory region or in a region that is physically
nonexist~nt.
The executio-n of th~ branch does not cause a trap un less
the instruction that is actually to follow the branch instruc-
tion is in a protected or nonexistent memory region. Traps
do not occur because of any anticipation on the part of the
hardware.
A nonallowed operation trap condition during execution of
a branch instruction wi II occur for the following reasons;
1.
The branch instruction -is indirectly
addressed~
and the
branch conditions are satisfied, but the address of the
location containing the direct address is either non-
existent or unavai lable for read access fo the program
in the slave mode.
2. The branch instruction is unconditional (or the branch
is conditional and the condition for the branch is satis-
fied), but the effective address of the branch instruc-
tion is either nonexistent or unavailable for instruction
or read access to the program (in slave -or master-
protected mode).
If
either of the above situations occurs, the basic processor
aborts execution of the branch instruction and executes a
nonallowed operation trap.
Prior to the time that an instruction is accessed from mem-
ory for execution, bit positions 15-31 of the program status
words contain the virtual address of the
instruction~
referred
to as the instruction address. At this time, the basic pro-
cessor traps to location X ' 40 ' if the actual address of the
instruction is nonexistent or instruction-access protected.
If the instruction address is existent and is not instruction-
access protected, the instruction is accessed and the in-
struction address portion of the program status words is
incremented by 1, so that it now contains the virtual address
of the next instruction in sequence {referred to as th~ up-
dated instruction address}.
If a trap condition occurs during the execulion sequence of
any instruction, the basic proces~r decrements the updated
instruction address by 1 and then traps to the location as-
signed to the trap condition.
If
neither a trap condition
nor a satisfied branch condition occurs during the execution
of an instruction, the next instruction is accessed from the
location pointed to by the updated instruction address.
If
a satisfied branch condition occurs during the execution of
a branch instruction (and no trap condition occurs), the
next instruction is accessed from the location pointed to by
the effective address of the branch instruction.