Xerox 560 Reference Manual page 46

system.
If the basic processor is in the map mode, the
program address wi
II
already have been modified by the
memory map to generate an actual (but nonexistent) ad-
dress. (See Table 5 for possible changes to registers and
memory locations later in this chapter.) The operation of
the X PSD or PSS in location X
140 1
is as follows:
1. Store the current PSWs.
2. Store general registers if PSS.
3. Load the new PSWs.
4. Modify the new PSWs.
a. Set CC2 to one. The other condition code bits
remain unchanged from the values loaded from
memory.
b.
If bit position 9 (AI) of the XPSD or PSS instruc-
tion contains a one, the program counter is incre-
mented by four. If AI contains a zero, the program
counter remains unchanged from the value loaded
from memory.
PRIVILEGED INSTRUCTION IN SLAVE MODE
An attempt to execute a privi leged instruction while the
basic processor is in the slave mode causes a trap to loca-
tion X '
40 '
before the privi leged operation is performed.
No general registers or memory locations are changed, and
the PSWs point to the instruction trapped. The operation
of the XPSD or PSS in trap location X '
40 '
is as follows:
1 • Store the current PSWs.
2. Store general registers if PSS.
3. Load the new PS'vVs.
a. Set CC3 to one. The other condition code bits
remain unchanged from the values loaded from
memory.
b.
If bit position 9 (AI) of the XPSD or PSS contains
a one, the program counter is implemented by two.
If AI contains a zero, the program counter remains
unchanged from the values loaded from memory.
MEMORY PROTECTION VIOLA nON
A memory protection violation occurs because of a memory
map access control bit violation (by a program executed
in slave mode or master-protected mode using the mem-
ory map). When memory protection violation occurs, the
basic processor aborts execution of the current instruction
40 Trap System
without changing protected memory and traps to location
X '
40
I
•
Refer to Table 5 for possible changes to registers
and memory locations. (The virtual page address that caused
the violation is in the fourth PSW word.) The operation of
the XPSD or PSS in trap location X ' 40
1
is as follows:
1 • Store the current PSWs.
2. Store general registers if PSS.
3. Load the new PSWs.
4. Modify the new PSWs.
a. Set CC4 to one. The other condition code bits
remain unchanged from the values loaded from
memory.
b. If bit position 9 (AI) of the XPSD or PSS contains
a one, the program counter is incremented by one.
If AI contains a zero, the program counter remains
unchanged from the va lue loaded from memory.
WRITE LOCK VIOLATION
A memory write lock violation occurs when an instruction
(program in master, master-protected, or slave mode) tries
to alter the contents of a write-protected memory page. If
a write lock violation occurs, the basic processor aborts ex-
ecution of the current instruction without changing protected
memory and traps to location X
140 1 •
(Refer to Table 5 for
possible changes to registers and memory locations.) (The
virtual page address that caused the violation is the fourth
PSW word.) The operation of the XPSD or PSS in trap lo-
cation X ' 40 ' is as follows:
1 . Store the current PSWs.
2. Store genera
I
reg is ters if PSS.
3. Load the new PSWs.
4. Modify the new PSWs.
a. Set CC3 and CC4 to ones. The other condition
code bits remain unchanged from the values loaded
from memory.
b.
If bit position 9 (AI) of the X PSD or PSS contains
a one, the program counter is incremented by
three. If AI contains a zero, the program counter
remains unchanged from the value loaded from
memory.