Xerox 560 Reference Manual page 125

Table 9. Status Word 0
Field Bits Comments
0
Reserved
1 Power status
2-7
Memory un i t error cod e
8-9
Memory type
Ports 10 Port 1 enabled
11
Port 2 enabled
12
Port 3 enabled
13 Port 4 enabled
14 Port 5 ena bl ed
15 Port 6 enabled
16
Port 1 serv iced
17 Port 2 serviced
18 Port 3 serviced
19 Port 4 serviced
20 Port 5 serviced
21 Port 6 servi ced
Memory fau
I
t 22 0
types
23 Uncorrectable memory unit error
24 Memory module selection error
,..e:
A 1.1. ____ . _____ !L __________
Lv
/",,\UUIC;:);:) pUllly CliVI
26 Data in parity error
27 Write lock parity error
28 Port selection error
29 Undefined operation
30 Control error
31 Multiple error
For IIread and inhibit parityll operations, the status of the
word loaded (if any) is stored in the condition code bits at
the conclusion of execution as follows:
CC 1: Memory Parity Error (from memory)
CC2: Data Bus Check (from CPU)
CC3: Parity Bit (from memory)
CC4: 0
T abl e 10. Status Word 1
Field Bits Comments
0 Interleave switch ON
1-3
Memory un it size:
000 8K
001 16K
010
24K
011
32K
100 40K
101 48K
110 56K
111 64K
4-6 Memory unit number (binary code)
Starting 7 Starting address bit 12
Address
8 Starting address bit 13
9 Starting address bit 14
10 Starting address bit 15
11 Starting address bit 16
12 Starting_ address bit 17
13
Starting address bit 18
14
Reserved
15-31 Address received, bits 15-31
WAIT
WAIT
(Word index al ignment, privileged)
WAIT causes the basic processor to cease all operations until
an interrupt activation occurs, or until the operator puts
the basic processor in the IDLE mode and then back to RUN
(see Chapter 5). The instruction address portion of the PSWs
is updated before the basic processor begins waiting; there-
fore, while it is waiting, the INSTRUCTION ADDRESS indi-
cators contain the virtual address of the next location in
ascending sequence after WAIT and the contents in the next
location are displayed in the DISPLAY indicators on the
processor control console.
If any input/output operations
are being performed when WAIT is executed, the operations
proceed to their normal termination.
When an interrupt activation occurs while the basic pro-
cessor is waiting, it processes the interrupt-servi cing routine.
Normally, the interrupt-servicing routine begins with an
XPSD instruction in the interrupt location, and ends with
an LPSD instruction at the end of the routine. After the
LPSD instruction is executed, the next instruction to be ex-
ecuted in the interrupted program is the next instruction in
sequence after the WAIT instruction. If the interrupt is to a
Control Instructions 119