Dialogue Between The Basic Processor And The Interrupt System During An; Dialogue During An Interrupt-Exiting Sequence; Physical Organization; Interrupt Groups - Xerox 560 Reference Manual

basic processor to execute the contents of the assigned
interrupt location as the next instruction. (Interrupt loca-
tions are defined in II Physical Organization ll , later in this
chapter.) The instruction address portion of the program sta-
tus ~ords (PSWs) remains unchanged unti I the instruction in
the interrupt location is executed.
The instruction in the interrupt location must be one of the
following: XPSD, PSS, MTS, MTH, or MTW. If the execu-
tion of any other instruction in an interrupt location is at-
tempted as the result of an interrupt level advancing to the
conditions for acknowledgment, an instruction exception
trap occurs.
The use of the privileged instruction XPSD or PSS in an in-
terrupt location permits an interrupt-servicing routine to
save the entire current machine environment. If working
registers are needed by the routine and additional register
blocks are avai lable, the contents of the current register
block can be saved automatically with no time loss. This
is accomplished by changing the value of the register pointer
(using the LOAD REGISTER POINTER instruction), which
results in the assignment of a new block of 24 registers to
the routine. The instruction LOAD REGISTER POINTER
(LRP) is described in Chapter 3, IIControl Instructions ll •
An interrupt level remains in the active state until it is
cleared (removed from the active state and returned to the
disarmed or armed state) by the execution of the LPSD, PlS,
or WD instruction. An interrupt-servicing routine can itself
be interrupted (whenever a higher priority interrupt level
meets all the conditions for becoming active) and then con-
tinued (after the higher priority interrupt is cleared). How-
ever, an interrupt-servicing routine cannot be interrupted
by an interrupt of the same or lower priority as long as the
higher priority interrupt level remains in the active state.
Any signals received by an interrupt level in the active
state are ignored. Norma lIy, the interrupt-servicing rou-
tine clears its interrupt level and transfers program control
back to the point of interrupt by means of an LPSD instruc-
tion with the same effective address as the XPSD instruc-
tion in the interrupt location.
DIALOGUE BETWEEN THE BASIC PROCESSOR AND
THE INTERRUPT SYSTEM DURING AN INTERUPT-
ENTERING SEQUENCE
When an interrupt level is ready to be moved to the active
state, a dialogue takes place between the interrupt system
and the basic processor. This dialogue takes place over the
processor bus and involves the Processor Interface (PI) asso-
ciated with the processor cluster of which the basic proces-
sor is a member. When the processor bus becomes avai lable
and the basic processor is ut un interruptible point, the in-
terrupt system transmits the interrupt address to the basic
processor. It initiates its interrupt actions (i.e., executes
the instruction in the interrupt location and services the
interrupt at the appropriate time to avoid race conditions,
and communicates with the interrupt system with an indi-
cation to move the level to the active state. This latter
32 Centra I ized Interrupts
transmission is delayed until the new inhibit states of the
basic processor are known; these states are transmitted to
the interrupt system so the latter can record the new basic
processor status.
DIALOGUE DURING AN INTERRUPT-EXITING SEQUENCE
When the basic processor exits an interrupt-servicing rou-
tine, it must notify the interrupt system to move the interrupt
level associated with that routine from the active state to
either the armed or disarmed state. To do this it must gain
access to the processor bus and the interrupt system, either
of which maybe busy at the time access is requested. When
communication with the interrupt system is established, the
basic processor transmits information for setting the level
state to armed or disarmed, and new inhibit states it has as-
sumed as a result of the exit operation.
PHYSICAL ORGANIZATION
Up to 62 interrupt levels are available, each with a unique
location (see Table 2) assigned in the System Control Pro-
cessor, and with a unique priority. The basic processor can
selectively arm, enable, or arm and enable any interrupt
level. The basic processor can also IItriggerll any interrupt
level (supply a signal at the same physical point where the
signa I from the externa I source wou Id enter the interrupt
level). The triggering of an interrupt permits testing spe-
cial systems programs before the special systems equipment
is available. The basic processor also permits an interrupt-
servicing routine to defer a portion of the processing asso-
ciated with an interrupt level by processing the urgent
portion of an interrupt-servicing routine, triggering a lower
priority level (for a routine that handles the less urgent
part), then clearing the high-priority interrupt level so that
other interrupts can occur before the deferred interrupt re-
~
___
~_ :~
_____
~~_..J
~I"'V"~" ,~
1""
v\.. ........ u.
INTERRUPT GROUPS
Interrupt levels are organized in standard group configura-
tions that are connected in a predetermined and fixed pri-
ority chain (see Table 2 and Figure 11). The priority of each
level within a group is fixed; the first level has the highest
priority and the last level has the lowest.
INTERNAL INTERRUPTS
Standard internal interrupts are provided with the system
and include all group D levels (interna I override
t
counter-
equa Is-zero, and I/O).