Xerox 560 Reference Manual page 111

II, EI) are generated by
II
ORing" the old CI, II, EI bits
with the contents of bits 37, 38, and 39 of the PSWs as
pu
II
ed from the memory stack.
The clearing and arming or disarming the highest priority
interrupt level currently active is dependent upon the
coding of the CL and AD flags (bit positions 10 and 11,
respectively) of the PLS instruction. If the CL flag is a 0
7
the interrupt level is not affected. If the CL flag fs-a 1
and the AD flag is a
Or
the interrupt level is set to the dis-
armed state. If the CL flag is a 1 and the AD flag is a
1r
the interrupt level is set to the armed state. Note that -if
the interrupt level is to be
modifie~
(CL flag is set to a 1),
the instruction maybe delayed unti
I
the interrupt system is
avai lable. -
Summary description of CL and AD flags and effect on in--
terrupt level and PDF flag follows:
Bit Positions
10 (CL)
o
o
11
(AD)
o
o
Function
No effect upon interrupt level
or PDF flag.
Reset PDF flag
Clear and disClrm interrupt level
Clear and arm interrupt level
If the initial Word Count is
zero
r
default PSWs are loaded -
from real memory locations 2 and 3 and the other parameters
of the Status Stack Pointer Doubleword are not effective
and no parameters are affected.
Portions of the new PSWs (interrupt inhibit group bits and
the Register Block Pointer) may be selected or generated in
the following manner:
If the LP flag (bit 8) of the PSL instruction is a
1r
the new
Register Block Pointer wi
II
be as obtained from the default
PSWs. If the LP flag is a 0, the Register Block Pointer of
the old PSWs is retained as the Register Block Pointer for
the new PSWs.
The CI, II, and EI bits of the old PSWs are "ORed
II
with
the contents of bit positions 37,
38
r
and 39 of the default
PSWs to generate the CI, II, and EI bits of the new PSWs.
Depending upon the coding of the CL and AD flags (bit
positions
10 and 11, respectively) of the PLS instruction,
the highest priority interrupt level currently in the active
state may be modified. If the CL flag is a 0, the interrupt
level is not affected. If the CL flag
is
a
1
and the AD flag
is a 0, the interrupt level is cleared and placed into the
disarmed state.
If
the CL flag is a 1 and the AD flag is
a 1, the interrupt level is cleared and placed into the
armed state. Note that if the interrupt_level is to be
modified (i. e., the CL flag is a 1), the instruction may be
delayed unti
I
the interrupt system is avai lab Ie.
A summary description of the action on the interrupt levei
as a function of the C1 and AD .flag is as follows:
Bit Positions
10
(CL)
o
o
11
(AD)
o
o
Function
No effect upon interrupt level
or PDF flag
Reset PDF flag
Clear and disarm interrupt level
Clear and arm interrupt level
If the initial Word Count within the Status Stack Pointer
Doubleword is less than 28 cmd not equal to 0, the basic
processor traps to location
X'4D~
(instruction exception
trap) without loading-any new status or affecting the pa-
rameters of the Status Stack Pointer Doubleword and the
r-CC2 bit is set to
1.
Affected: If word count
~
28,
(PSWs), CC,
Status Stack Pointer
Doubleword
Interrupt System if
(1)10=1.
Traps: Instruction excep-
tion, if word count
is less than 28 and
not 0; nonexistent
instruction if
bit
0=1.
If word count = 0, (PSWs),
ec,
and Inferrupt
System, if 1(10)=1.
(PSWs) and CC
ED
O
_
3
-CC;
ED 5-7 - FS,
FZ,
FN;
ED
8
-MS;
-ED
9
-MM;
ED
lO
- DM;
ED
11
-AM;
ED 15 - 31 -
IA;
ED
32
_
35
-WK
ED37-39 u CI, II,-EI -CI, II, EI
(Note: "u" represents inclusive OR. )
[D
56
-
59
- RP only if (1)8= 1
ED
60
-RA
ED
61
-MA
push-Down Instructions (Privi leged) 105