1L. Interrupt Priority Chain - Xerox 560 Reference Manual

1st Priority
2nd Priority 3rd Priority
Internal External
Counter-
Override
Override Equals-Zero
Interrupts Interrupts
Interrupts
4th Priority 5th Priority
6th Priority
External External
I/o
Interrupts
Group 2 Group 4
Interrupts Interrupts
7th Priority
External
Group 5
Interrupts
Figure 11. Interrupt Priority Chain
Internal Override Group (Locations X '52 1 through X ' 571).
The six interrupt levels of thi!> group always have the highest
priority in the system. The four count-pulse interrupt levels
are triggered by pulses from clock sources. Counter 4 has
a constant frequency of 500 Hz. Counters 1, 2, and 3 can
be individua IIy set to any of four manually switchable fre-
quencies - the commercial line frequency, 500 Hz, 2000 Hz,
or a user-supplied external signal - that may be different
for each counter. Each of the count pulse interrupt loca-
tions must contain one of the modify and test instructions
(MTB, MTH, or MTW), an XPSD, or a PSS instruction.
H/'-_._ l.'- ____ J!C! __ l.! __ f_C .. L _ _ CC __ L! .• _ L ..
L_
L_IC ... __ J __
VYIII::I1 1111::
IIIUUIII~UIIUIi
\UI 1111::
1::111::~IIVI::
Uyll::, IIUIIVVUIU, UI
word) causes a zero result, the appropriate counter-equals-
zero interrupt level (see "Counter-Equals-Zero Group") is
triggered.
Note: Count pulse interrupt level 4 is a subjective time
counter with the following special attribute: When
the instruction in location X ' 55 1 is executed as the
result of an interrupt, it must be an MTB, MTH, or
MTW; otherwise, an instruction exception trap
(X ' 40 ' ) will occur.
The internal override group also contains a processor fault
and a memory fault interrupt level. Both locations norma IIy
contain an XPSD or a PSS instruction. The processor fault
interrupt level is triggered by a signal when certain fault
conditions are detected. A POLR instruction must be used
to reset the fault. The memory fault interrupt level is
34 Centralized Interrupts
triggered by a signal that the memory generates when it
detects certain fault conditions. An LMS instruction must
be used to reset the fault. (See "Trap System" later in
this chapter for further information on processor and memory
faults.)
Counter-Equals-Zero Group (Locations X 158 1 through X '5B ' ).
Each interrupt I eve lin the counter-equa Is-zero group is as-
sociated with a corresponding count-pulse interrupt level in
the internal override group. When the execution of a mod-
!c .. __
J
L __ L
! __
.L_ •• _L! __ : _ ..
L ___ •. _ .. __ •. 1 __
!_j. ___ .. _j.
1 ___ .. : __
I l y UIIU IC;)I
III;)IIU~IIUII
III IIIC
~UUIII-I"UI;)C
IIIICIIUI"I
IU~UIIUII
causes a zero result in the effective byte, halfword, or word
location, the corresponding counter-equals-zero interrupt
level is triggered. The counter-equals-zero interrupt loca-
tions normally contain an XPSD or a PSS instruction and
they can be i nh ib i ted or permitted as a group.
If
bit 37
(CI) of the current PSW contains a zero, the counter-equals-
zero interrupt levels are allowed to interrupt the program
being executed. If the CI bit contains a one, the counter-
equals-zero interrupt levels are inhibited from being allowed
to interrupt the program. These interrupt levels wait until
the C I bit is reset to zero and then interrupt the program ac-
cording to priority.
Input/Output Group (Locations X '5C through X ' 5F'). This
interrupt group comprises the input/output (I/O) interrupt
level, the control panel interrupt level, and two levels re-
served for future use. The I/O interrupt level accepts inter-
rupt signa Is from the
I/o
system. The
I/O
interrupt location