Xerox 560 Reference Manual page 97

of the destination byte that caused the instruction to
terminate. If no translation byte is found that satisfies
the above condition after the specified number of destina-
tion bytes have been compared, TTBS terminates with CC4
reset to O. In no case does the TTBS instruction change
the source byte stri ng.
Affected: (R), (Rul), CC4 Trap: Instruction exception
If
translated (SBS) n mask
I
0, translated (SBS) n mask-
mask and stop
If translated (SBS) n mask = 0, continue
Condition code settings:
2 3 4 Result of TTBS
- 0 Translation bytes and the mask do not com-
pare ones any place.
The last translation byte compared with the
mask contained at least one 1 corresponding
to a 1 in the mask.
The R field of the TTBS instruction must be an even value
for proper operation of the instruction; if the R field of TTBS
is an odd value, the instruction traps to location X l 4D I
,
instruction exception trap.
If TTBS is indirectly addressed, it is treated as a nonexistent
Insrrucrion. The basic processor unconciiTionaiiy aborts
execution of the instruction (at the time of operation code
decoding) and traps to location X
I
40
1
with the contents of
register R and the destination byte string unchanged.
See IITraps By Byte String Instructions" (in this section) for
other trap conditions. Note that the check for access trap
conditions is done only for the source byte string.
Case I, even, nonzero R field (Rul=R+1)
Contents of register R:
Contents of register R+l:
Count
I
! :
Destination
~ddress
I
o
1 2 314 5 6 7 8 9 10 11112 13 14 15 16 17 18 19120 212223;2425262712829 30 31
The destination byte string begins with the byte location
pointed to by the destination address in register R + 1 and
is C bytes in length. The source byte string (translation
table) begins with the byte location pointed to by the dis-
placement in TTBS plus the source address in register R.
Case II, odd R field
Because of the interruptible nature of TRANS LATE AND
TEST BYTE STRING the instruction traps with the contents
of register R unchanged when an odd-numbered general reg-
ister is specified by the R field of the instruction word.
Case III, zero R field (Rul=1)
Contents of register 1:
The destination byte string begins with the byte location
pointed to by the destination address in register 1 and is
C bytes in length. The source byte string (translation table)
begins with the location pointed to by the displacement in
TTBS. In this case, the instruction automatically provides
a mask of eight lis. (This is an exception to the general
rule, used in the other byte-string instructions, the reg-
ister 0 provides all
OIS
as its contents. )
EBS
EDIT BYTE STRING
(Immedi ate displacement, continue after interrupt)
63
I
R
I
: DisPlacem~nt
I
7 8 9 10 11 12 13 14 15 16 17 18 19120 21 22 23 24 25 26 27128 29 30 31
o
1 2
EDIT BYTE STRING converts a decimal information field
from packed decimal format to zoned decimal EBCDIC for-
mat, under control of the editing pattern in the destination
byte string, and replaces the destination byte string with the
edited, zoned result. (See "Decimal Instructions", "Packed
Decimal Numbers", and "Zoned Decimal Numbers" for
a description of packed and zoned decimal formats.) EBS
proceeds one byte at a time, starting with the first (most
significant) byte of the editing pattern, and continues
unti
I
all bytes in the editing pattern have been processed.
The fill character, contained in bit position 0-7 of regis-
ter R, replaces the pattern byte under specifi ed conditions.
More than one decimal number field can be edited by a
single EBS instruction if the pattern in memory is, in fact,
a series of patterns corresponding to a series of number
fields. In such cases, however, after the EBS instruction is
completed, the condition code indicates the result of the
last decimal number field processed and register 1 contains
the byte address (or the byte address plus 1) of the last sig-
nificance indicator in the edited destination byte string.
(This allows the insertion of a floating dollar sign, etc.,
with a subsequent instruction. )
R must be an even value (excluding 0) for proper operation
of the instruction; if R is an odd value or equal to zero, the
basic processor traps to location X I 4D I
,
instruction excep-
tion trap, with the contents in register R unchanged.
Byte-String Instructions 91