Pll Circuits - Icom IC-M72 Service Manual

4-2-3 TRANSMIT AMPLIFIERS (RF UNIT)
The VCO output signal is amplifi ed to transmit output power
level by the transmit amplifi ers.
The transmit signal from the TX/RX switch (D50) is applied
to the buffer amplifier (Q50). The amplified transmit signal is
amplified to the transmit output level by the pre-driver (Q53)
and power amplifier (Q54). The power-amplified transmit
signal is passed through the TX power detector of APC circuit
(D91), antenna switch (D52, D90 and D353 are ON), TX
power detector for transmit indicator (D80) and LPF (as a
harmonic filter; L81, L82, C80, C83−C86, C89, C226) before
being applied to the antenna connector (CHASSIS; J1).
4-2-1 APC CIRCUIT (RF UNIT)
The APC (Automatic Power Control) circuit stabilizes trans-
mit output power to prevent transmit output power level change
which is caused by load mismatching or heat effect, etc,. The
APC circuit also selects transmit output power from high,
middle and low power.
The power detector circuits (D91) detects the transmit output
and converts it into DC voltage which is in proportion to the
transmit output power level. The detected voltage is applied
to the differential amplifi er (IC50, pin 3). The transmit power
setting voltage "PCON" is applied to another input terminal
(pin 1) as the reference voltage.
The differential amplifi er compares the detected voltage and
reference voltage, and the difference of the voltage is output
from pin 4. The output voltage controls the bias of the buffer
amplifi er (Q50), pre-driver (Q53) and power amplifi er (Q54)
to reduce/increase the gain of transmit amplifi ers for stable
transmit output power.
The change of transmit power is carried out by the change
of reference voltage "PCON" and "LOW."

• PLL CIRCUITS

PLL IC (RF UNIT; IC1)
7
"UNLK"
3
"PLST"
4
"SCK"
5
"SDATA"
15
X1
16
17
LPF
to the FM IF IC
(MAIN UNIT; IC170, pin 2)
Prescaler
Programmable
DATA interface
counter
Reference Phase
counter detector
4-3 PLL CIRCUITS
4-3-1 VCO CIRCUIT (RF UNIT)
The VCO (Q21, Q22, D21−D23) generates the both of trans-
mit signal and LO signals for the 1st IF conversion. The VCO
output signals are buffer-amplified by Q23 and Q24.
While transmitting, the VCO output signal is applied to the
transmit amplifiers via TX/RX switch (D50 is ON, D51 is OFF).
While receiving, the VCO output signals are applied to the 1st
mixer (Q150) via the TX/RX switch (D50 is OFF, D51 is ON)
the BPF (L26, C122, C123, C130, C131), to be mixed with
the received signals to produce the 21.7 MHz 1st IF signal.
A portion of the VCO output is applied to the PLL IC (IC1,
pin 19) via the buffer amplifier (Q25) and LPF (L20, R20,
C20−C22).
4-3-2 PLL CIRCUIT (RF UNIT)
The PLL circuit provides stable oscillation of the transmit
frequency and receive 1st LO frequency. The PLL output
frequency is controlled by the divided ratio (N-data) from the CPU.
The buffer-amplified signals from the LPF (L20, R20, C20−
C22) are applied to the PLL IC (IC1, pin 19). The applied
signals are divided at the prescaler and programmable
counter according to the "SDATA (SDATAO)" signal from
the CPU (MAIN UNIT; IC360, pin 10). The divided signal is
phase-compared with the reference frequency signal which is
divided by reference counter, at the phase detector.
The phase difference is output from pin 13 as a pulse type
signal after being passed through the charge pump. The
output signal is converted into the DC voltage (lock voltage) by
passed through the loop filter (R8−R10, R22, C10, C11, C24,
C25). The lock voltage is applied to the variable capacitors (D22,
D23) of the VCO (Q21, Q22, D21−D23) and locked to keep
the VCO frequency constant.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the VCO oscillating frequency.
Buffer
LPF
Q25
19
Loop
13
Charge
pump
filter
Q22, Q37, D21–D23
4 - 3
Buffer
Q24
to the TX/RX switch (D50, D51)
Buffer
Q23
VCO