Table 17. Supported Err2 Timeout Sensor Offsets - Intel S2600IP Technical Product Specification

Platform Management OverviewIntel® Server Board S2600IP and Intel® Workstation Board W2600CR TPS
Refer to the applicable platform BMC EPS as to the details of what population rules must be
followed.
4.3.4.3 ERR2 Timeout Monitoring
The BMC supports an ERR2 Timeout Sensor (1 per CPU) that asserts if a CPU's ERR2 signal
has been asserted for longer than a fixed time period (> 90 seconds). ERR[2] is a processor
signal that indicates when the IIO (Integrated IO module in the processor) has a fatal error
which could not be communicated to the core to trigger SMI. ERR[2] events are fatal error
conditions, where the BIOS and OS will attempt to gracefully handle error, but may not be
always do so reliably. A continuously asserted ERR2 signal is an indication that the BIOS
cannot service the condition that caused the error. This is usually because that condition
prevents the BIOS from running.
When an ERR2 timeout occurs, the BMC asserts/deasserts the ERR2 Timeout Sensor, and
logs a SEL event for that sensor. The default behavior for BMC core firmware is to initiate a
system reset upon detection of an ERR2 timeout. The BIOS setup utility provides an option to
disable or enable system reset by the BMC for detection of this condition.
IPMI Sensor Characteristics
1. Event reading type code: 03h (Generic – digital discrete)
2. Sensor type code:
3. Rearm type:
Offset
01h
4.3.4.4 CATERR Sensor and Market Segment ID (MSID) Mismatch
The BMC supports a CATERR sensor for monitoring the system CATERR signal.
The CATERR signal is defined as having 3 states; high (no event), pulsed low (possibly fatal
may be able to recover), and low (fatal). All processors in a system have their CATERR pins
tied together. The pin is used as a communication path to signal a catastrophic system event to
all CPUs. The BMC has direct access to this aggregate CATERR signal.
The BMC only monitors for the "CATERR held low" condition. A pulsed low condition is ignored
by the BMC.
If a CATERR-low condition is detected, the BMC logs an error message to the SEL against the
CATERR sensor and then queries each CPU to determine if it was due to an MSID mismatch
condition. An MSID mismatch occurs if a processor is installed into a system board that has
incompatible power capabilities. The MSID mismatch condition is indicated in a processor
machine check MSR. If PECI is non-functional (it isn't guaranteed in this situation), then MSID
mismatch can't be detected in that case.
If the CATERR is due to an MSID mismatch, then the BMC will log an additional SEL log
against the MSID Mismatch sensor, light the CPU fault LED, emit a beep code, and let the
system hang. Please refer Table 9 (BMC Beep Codes) for beep code details. If no MSID
58
07h (Processor)
Auto

Table 17. Supported ERR2 Timeout Sensor Offsets

Description
State asserted
Intel order number G34153-003
Event Logging
Assertion and deassertion
Revision 1.1