Table 6. Dimm Nomenclature - Intel S2600IP Technical Product Specification

Intel® Server Board S2600IP and Intel® Workstation Board W2600CR TPS
3.2.2.2 Memory Population Rules
Note: Although mixed DIMM configurations are supported, Intel only performs platform
validation on systems that are configured with identical DIMMs installed.
Each processor provides four banks of memory, each capable of supporting up to 2 DIMMs.

DIMMs are organized into physical slots on DDR3 memory channels that belong to
processor sockets.

The memory channels from processor socket 1 are identified as Channel A, B, C and D.
The memory channels from processor socket 2 are identified as Channel E, F, G, and H.

The silk screened DIMM slot identifiers on the board provide information about the
channel, and therefore the processor to which they belong. For example, DIMM_A1 is
the first slot on Channel A on processor 1; DIMM_E1 is the first DIMM socket on
Channel E on processor 2.

The memory slots associated with a given processor are unavailable if the
corresponding processor socket is not populated.

A processor may be installed without populating the associated memory slots provided a
second processor is installed with associated memory. In this case, the memory is
shared by the processors. However, the platform suffers performance degradation and
latency due to the remote memory.

Processor sockets are self-contained and autonomous. However, all memory subsystem
support (such as Memory RAS, Error Management,) in the BIOS setup are applied
commonly across processor sockets.
®
On the Intel Server Board S2600IP and Intel
slots is provided (2 CPUs – 4 Channels/CPU, 2 DIMMs/Channel). The nomenclature for DIMM
sockets is detailed in the following table:
Processor Socket 1
(0) (1)
Channel A Channel B
A1 A2 B1 B2
Revision 1.1
®

Table 6. DIMM Nomenclature

(2) (3)
Channel C Channel D
C1 C2 D1 D2
Intel order number G34153-003
Workstation Board W2600CR a total of 16 DIMM
Processor Socket 2
(0) (1)
Channel E Channel F
E1 E2 F1
Functional Architecture
(2)
Channel G Channel H
F2 G1 G2 H1
(3)
H2
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