Figure 11: Atm Ethernet Vlan Interworking Packet Structure; Figure 12: Ccc To Stacked Vlan Translation - Juniper JUNOS OS 10.4 Manual

Junos OS 12.1 MX Series 3D Universal Edge Routers Solutions Guide
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78
Because of the translation, the flow of packets and frames between PE1 (the M Series
router) and PE2 (the MX series router) routers is not symmetrical, as is shown in
11 on page 78.

Figure 11: ATM Ethernet VLAN Interworking Packet Structure

1. PE1 PE2
L3 Ethertype SA DA
8 bytes" is an ATM cookie added by an M Series ATM pic.
The first 2 bytes of this ATM cookie is inner VLAN.
2. PE2 PE1
L3 Ethertype SA DA
For PE1 to PE2 traffic, the 8 bytes following the MPLS header is an ATM cookie added by
the M Series ATM PIC. The first two bytes are the inner VLAN tag, which is why the field
extends to the right of the figure.
The traffic between PE2 and CE2 is a normal flow of stacked Ethernet frames.
You can also configure a CCC with remote interface switch or Layer 2 circuit over
Aggregated Ethernet on the MX Series router (PE2). When CCC is configured for
Aggregated Ethernet, the flow of packets is as shown in

Figure 12: CCC to Stacked VLAN Translation

1. CCC to stacked-vlan
L3 Ethertype SA DA
L3 Ethertype Ivlan
2. Stacked-vlan to CCC
L3 Ethertype Ivlan
L3 Ethertype SA DA
ATM Ethernet Interworking
Configuring MX Series Router ATM Ethernet Interworking on page 79
Inner VLAN MPLS Ethernet
Inner VLAN MPLS Ethernet
Figure 12 on page
Inner VLAN MPLS Ethernet
Ovlan SA DA
Ovlan SA DA
Inner VLAN MPLS Ethernet
Copyright © 2012, Juniper Networks, Inc.
Figure
78.