Setting Up The Master Clock (Mclk) - Analog Devices EVAL-AD1974AZ User Manual

UG-046
POWER SELECTION
JP5 JP6
Figure 5. AD1974 Power Jumpers

SETTING UP THE MASTER CLOCK (MCLK)

The AD1974 evaluation board has a series of jumpers that give
the user great flexibility in the MCLK clock source for the
AD1974. MCLK can come from five sources: passive crystal,
active oscillator, external clock in, and two header connections.
Note that the CPLD on the board must have a valid clock
source; the frequency is not critical. These jumper blocks can
assign this CPLD clock. Most applications of the board use
MCLK from either the oscillator or one of the header (HDR)
inputs. Figure 6 to Figure 7 show the on-board active oscillator
disabled so that it does not interfere with the selected clock. The
clock feed to the CPLD comes directly from the clock source.
Note that, if the HDR connectors are to be driven with MCLK
from a source on the evaluation board, SW2 and/or SW3 must
be switched from the IN position to the OUT position.
193X_MCLKI
DISABLE
JP18
JP19
1938_MCLKI
JP22
R160
L7
C158
JP23
CPLD
U21
JP25
HDR2
JP27
OSC DISABLE
HDR1
JP28
EXT
CLK
JP29
8416
JP30
HDR2
JP31
HDR1
Figure 6. Active On-Board Oscillator as Master; the AD1974 and
CPLD as Slaves
193X_MCLKI
DISABLE
JP18
JP19
1938_MCLKI
JP22
R160
L7
C158
JP23
CPLD
U21
JP25
HDR2
JP27
OSC DISABLE
HDR1
JP28
EXT
CLK
JP29
8416
JP30
HDR2
JP31
HDR1
Figure 7. HDR1 as MCLK Master; the AD1974, CPLD, and HDR2 as Slaves
JP7
JP20
C147
MCLKO
XTAL
J22
U18
Y1
193X_MCLKO
R167
R169
J23
R172
U22
R174
R175
C168
EXT CLK IN
C170
JP20
C147
MCLKO
XTAL
J22
U18
Y1
193X_MCLKO
R167
R169
J23
R172
U22
R174
R175
C168
EXT CLK IN
C170
1938_MCLKI
R160
L7
C158
OSC DISABLE
EXT
Figure 8. External Clock In as Master; the AD1974 and CPLD as Slaves
The MCLK configurations shown in Figure 9 and Figure 10 use
the AD1974 MCLKO port to drive the CPLD and, possibly, the
HDRs. The passive crystal runs the AD1974 at 12.288 MHz.
Figure 10 shows the MCLKI shut off; this is the case when the
PLL is set to LRCLK instead of to MCLK.
1938_MCLKI
R160
L7
C158
OSC DISABLE
EXT
Figure 9. Passive Crystal; the AD1974 Is Master; the CPLD Is Slave from
1938_MCLKI
R160
L7
C158
OSC DISABLE
EXT
Figure 10. LRCLK Is the Master Clock Using the PLL; MCLKI Is Disabled, and
Rev. 0 | Page 4 of 32
Evaluation Board User Guide
193X_MCLKI
DISABLE
JP18 JP20
C147
MCLKO
XTAL
JP19
U18
JP22
Y1
JP23
193X_MCLKO
CPLD
R167
U21
JP25
HDR2
R169
JP27
R172
HDR1
U22
JP28
CLK
R174 R175
JP29
8416
C168
C170
JP30
HDR2
JP31
HDR1
193X_MCLKI
DISABLE
JP20
JP18
C147
MCLKO
XTAL
JP19
U18
JP22
Y1
JP23
193X_MCLKO
CPLD
R167
U21
JP25
HDR2
R169
JP27
R172
HDR1
U22
JP28
CLK
R174 R175
JP29
8416
C168
C170
JP30
HDR2
JP31
HDR1
the MCLKO Port
193X_MCLKI
DISABLE
JP20
JP18
C147
MCLKO
XTAL
JP19
U18
JP22
Y1
JP23
193X_MCLKO
CPLD
R167
U21
JP25
HDR2
R169
JP27
R172
HDR1
U22
JP28
CLK
R174 R175
JP29
8416
C168
C170
JP30
HDR2
JP31
HDR1
CPLD Is Slave to the MCLKO Port
J22
J23
EXT CLK IN
J22
J23
EXT CLK IN
J22
J23
EXT CLK IN