Dalsa Spyder3 User Manual page 92

92
• FVAL—Frame Valid (FVAL) is defined HIGH for valid lines.
• LVAL—Line Valid (LVAL) is defined HIGH for valid pixels.
• DVAL—Data Valid (DVAL) is defined HIGH when data is valid.
• Spare— A spare has been defined for future use.
All four enable signals must be provided by the camera on each Channel Link chip. All
unused data bits must be tied to a known value by the camera. For more information on
image data bit allocations, refer to the official Camera Link specification located at
http://mv.dalsa.com.
Camera Control Signals
Four LVDS pairs are reserved for general purpose camera control. They are defined as
camera inputs and frame grabber outputs. Camera manufacturers can define these signals
to meet their needs for a particular product. The signals are:
• Camera Control 1 (CC1)
• Camera Control 2 (CC2)
• Camera Control 3 (CC3)
The camera uses the following control signals:
Table 19: DALSA Camera Control Configuration
CC1
CC2
CC3
Communication
Two LVDS pairs have been allocated for asynchronous serial communication to and from
the camera and frame grabber. Cameras and frame grabbers should support at least 9600
baud. These signals are
• SerTFG—Differential pair with serial communications to the frame grabber.
• SerTC—Differential pair with serial communications to the camera.
The serial interface will have the following characteristics: one start bit, one stop bit, no
parity, and no handshaking. It is recommended that frame grabber manufacturers supply
both a user interface and a software application programming interface (API) for using
the asynchronous serial communication port. The user interface will consist of a terminal
program with minimal capabilities of sending and receiving a character string and
sending a file of bytes. The software API will provide functions to enumerate boards and
send or receive a character string.
03-032-20059-01
EXSYNC, negative edge active
PRIN
Direction
Spyder3 Color Manual
DALSA