DFI G5M300-P User Manual page 73

Manual
3.1.3.2 CAS Latency Time
This field is used to select the local memory clock periods.
3.1.3.3 Active to Precharge Delay
The options are 5, 6 and 7.
3.1.3.4 DRAM RAS# to CAS# Delay
The options are 2 and 3.
3.1.3.5 DRAM RAS# Precharge
This field controls RAS# precharge (in local memory clocks).
3.1.3.6 DRAM Data Integrity Mode
The ECC (Error Checking and Correction) function is supported only
in x72 (72-bit) PC SDRAM DIMMs. If you are using x64 (64-bit) PC
SDRAM DIMMs, set this field to Non-ECC.
Non-ECC
ECC This option allows the system to recover from memory
failure. It detects single-bit and multiple-bit errors, then
automatically corrects single-bit error.
3.1.3.7 System BIOS Cacheable
When this field is enabled, accesses to the system BIOS ROM
addressed at F0000H-FFFFFH are cached, provided that the cache
controller is enabled. The larger the range of the Cache RAM, the
higher the efficiency of the system.
If you want better performance for your system
other than the one "by SPD", select "Manual" then
select the best option in the "CAS Latency Time"
and "Active to Precharge Delay fields.
Uses x64 PC SDRAM DIMM.
3
BIOS Setup
7 3