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AUTOMOTIVE 80C51FA/83C51FA
DC CHARACTERISTICS:
Symbol
Parameter
I
Logical 1 to 0 Transition Current
TL
(Ports 1, 2, and 3)
RRST
RST Pulldown Resistor
CIO
Pin Capacitance
I
Power Supply Current:
CC
Running at 12 MHz (Figure 5)
Idle Mode at 12 MHz (Figure 5)
Power Down Mode (I
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause noise pulses to be superimposed on the V
The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operations. In applications where capacitance loading exceeds 100 pFs, the noise pulse on the ALE
signal may exceed 0.8V. In these cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an Address Latch
with a Schmitt Trigger Strobe input.
2. Capacitive loading on Ports 0 and 2 cause the V
address lines are stabilizing.
3. See Figures 6 ±9 for test conditions. Minimum V
4. Typicals are based on limited number of samples, and are not guaranteed. The values listed are at room temperature and
5.0V.
5. Under steady state (non-transient) conditions, I
Maximum I
per Port Pin:
OL
Maximum I
per 8-Bit Port -
OL
Ports 1, 2, and 3:
Maximum Total I
for all Output Pins:
OL
If I
exceeds the test condition, V
OL
than the listed test conditions.
6. Contact Intel for design-in information.
8
(T
40 C to
125 C; V
A
e b
a
Min
40
)
PD
on ALE and PSEN to drop below the 0.9 V
OH
for Power Down is 2.0V.
CC
must be externally limited as follows:
OL
10 mA
Port 0:
26 mA
15 mA
71 mA
may exceed the related specification. Pins are not guaranteed to sink current greater
OL
5V
10%; V
0V) (Continued)
CC
SS
e
e
g
Typ
Max
Unit
265
650
A
b
b
100
225
K
10
pF
40
mA
15
mA
150
A
s of ALE and Ports 1 and 3.
OL
CC
Test Conditions
V
2V
IN
e
1MHz, 25 C
(Note 3)
specification when the
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