Analog Devices AD9883A Specification Sheet page 13

2-Wire Serial Register Map
The AD9883A is initialized and controlled by a set of registers, which determine the operating modes. An external controller is
employed to write and read the Control Registers through the 2-line serial interface port.
Write and
Hex Read or
Address Read Only Bits
00H RO 7:0
01H R/W 7:0
02H R/W 7:4
03H R/W 7:3
04H R/W 7:3
05H R/W 7:0
06H R/W 7:0
07H R/W 7:0
08H R/W 7:0
09H R/W 7:0
0AH R/W 7:0
0BH R/W 7:1
0CH R/W 7:1
0DH R/W 7:1
0EH R/W 7:0
Table VI. Control Register Map
Default Register
Value Name
Chip Revision
01101001 PLL Div MSB This register is for Bits [11:4] of the PLL divider. Larger values mean
1101 PLL Div LSB
01
001
01000 Phase Adjust
10000000 Clamp
Placement
10000000 Clamp
Duration
00100000 Hsync Output
Pulsewidth
10000000 Red Gain
10000000 Green Gain
10000000 Blue Gain
1000000 Red Offset
1000000 Green Offset
1000000 Blue Offset
0 Sync Control
1
0
0
0
0
0
0
Function
An 8-bit register that represents the silicon revision level.
Revision 0 = 0000 0000
the PLL operates at a faster rate. This register should be loaded first
whenever a change is needed. (This will give the PLL more time to
lock.) See Note 1 .
Bits [7:4] LSBs of the PLL divider word. See Note 1.
Bits [7:6] VCO Range. Selects VCO frequency range. (See PLL
description.)
Bits [5:3] Charge Pump Current. Varies the current that drives the
low-pass filter. (See PLL description.)
ADC Clock Phase Adjustment. Larger values mean more delay.
(1 LSB = T/32.)
Places the Clamp signal an integer number of clock periods after the trail-
ing edge of the HSYNC signal.
Number of clock periods that the Clamp signal is actively clamping.
Sets the number of pixel clocks that HSOUT will remain active.
Controls ADC input range (Contrast) of each respective channel.
Bigger values give less contrast.
Controls dc offset (Brightness) of each respective channel. Bigger
values decrease brightness.
Bit 7 – Hsync Polarity Override. (Logic 0 = Polarity determined by
chip, Logic 1 = Polarity set by Bit 6 in register 0Eh.)
Bit 6 – Hsync Input Polarity. Indicates polarity of incoming HSYNC
signal to the PLL. (Logic 0 = Active Low, Logic 1 = Active High.)
Bit 5 – Hsync Output Polarity. (Logic 0 = Logic High Sync, Logic 1 =
Logic Low Sync.)
Bit 4 – Active Hsync Override. If set to Logic 1, the user can select
the Hsync to be used via Bit 3. If set to Logic 0, the active interface
is selected via Bit 6 in register 14H.
Bit 3 – Active Hsync Select. Logic 0 selects Hsync as the active
sync. Logic 1 selects Sync-on-Green as the active sync. Note: The
indicated Hsync will be used only if Bit 4 is set to Logic 1 or if both
syncs are active, (Bits 1, 7 = Logic 1 in register 14H).
Bit 2 – Vsync Output Invert. (Logic 0 = No Invert, Logic 1 = Invert.)
Bit 1 – Active Vsync Override. If set to Logic 1, the user can select
the Vsync to be used via Bit 0. If set to Logic 0, the active interface
is selected via Bit 3 in register 14H.
Bit 0 – Active Vsync Select. Logic 0 selects Raw Vsync as the output
Vsync. Logic 1 selects Sync Separated Vsync as the output Vsync.
Note: The indicated Vsync will be used only if Bit 1 is set to Logic 1.
AD9883A