Analog Devices AD9883A Specification Sheet page 21

Data is read from the control registers of the AD9883A in a similar
manner. Reading requires two data transfer operations:
The base address must be written with the R/W bit of the slave
address byte LOW to set up a sequential read operation.
Reading (the R/W bit of the slave address byte high) begins at
the previously established base address. The address of the read
register autoincrements after each byte is transferred.
To terminate a read/write sequence to the AD9883A, a stop
signal must be sent. A stop signal comprises a low-to-high tran-
sition of SDA while SCL is high.
A repeated start signal occurs when the master device driving
the serial interface generates a start signal without first generat-
ing a stop signal to terminate the current communication. This
is used to change the mode of communication (read, write)
between the slave and master without releasing the serial inter-
face lines.
Serial Interface Read/Write Examples
Write to one control register
➥ Start Signal
➥ Slave Address Byte (R/W Bit = LOW)
➥ Base Address Byte
➥ Data Byte to Base Address
➥ Stop Signal
Write to four consecutive control registers
➥ Start Signal
➥ Slave Address Byte (R/W Bit = LOW)
SYNC STRIPPER
SOG
HSYNC IN
COAST
VSYNC IN
ACTIVITY
DETECT
SDA BIT 7 BIT 6 BIT 5
SCL
NEGATIVE PEAK COMP
CLAMP SYNC
PLL
ACTIVITY
DETECT
POLARITY
DETECT
➥ Base Address Byte
➥ Data Byte to Base Address
➥ Data Byte to (Base Address + 1)
➥ Data Byte to (Base Address + 2)
➥ Data Byte to (Base Address + 3)
➥ Stop Signal
Read from one control register
➥ Start Signal
➥ Slave Address Byte (R/W Bit = LOW)
➥ Base Address Byte
➥ Start Signal
➥ Slave Address byte (R/W bit = HIGH)
➥ Data Byte from Base Address
➥ Stop Signal
Read from four consecutive control registers
➥ Start Signal
➥ Slave Address Byte (R/W Bit = LOW)
➥ Base Address Byte
➥ Start Signal
➥ Slave Address Byte (R/W Bit = HIGH)
➥ Data Byte from Base Address
➥ Data Byte from (Base Address + 1)
➥ Data Byte from (Base Address + 2)
➥ Data Byte from (Base Address + 3)
➥ Stop Signal
BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
ACTIVITY
DETECT
SYNC SEPARATOR
INTEGRATOR
MUX 1
POLARITY
DETECT
HSYNC
CLOCK
MUX 2
GENERATOR
COAST
MUX 3
POLARITY
DETECT
MUX 4
AD9883A
ACK
VSYNC
1/S
HSYNC OUT
PIXEL CLOCK
AD9883A
SOG OUT
HSYNC OUT
VSYNC OUT