Intel X3330 - Xeon 2.66 Ghz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor Specification page 37

Implication: Due to this erratum, IA32_FIXED_CTR2 MSR will not return reliable counts after
returning from an Intel Deep Power-Down State.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAA70. Enabling PECI via the PECI_CTL MSR Does Not Enable PECI and May
Corrupt the CPUID Feature Flags
Problem: Writing PECI_CTL MSR (Platform Environment Control Interface Control Register) will
not update the PECI_CTL MSR (5A0H), instead it will write to the VMM Feature Flag
Mask MSR (CPUID_FEATURE_MASK1, 478H).
Implication: Due to this erratum, PECI (Platform Environment Control Interface) will not be enabled
as expected by the software. In addition, due to this erratum, processor features
reported in ECX following execution of leaf 1 of CPUID (EAX=1) may be
masked. Software utilizing CPUID leaf 1 to verify processor capabilities may not work
as intended.
Workaround: It is possible for the BIOS to contain a workaround for this erratum. Do not initialize
PECI before processor update is loaded. Also, load processor update as soon as
possible after RESET as documented in the RS – Wolfdale Processor Family BIOS
Writers Guide, Section 14.8.3 Bootstrap Processor Initialization Requirements.
Status: For the steppings affected, see the Summary Tables of Changes.
AAA71. INIT Incorrectly Resets IA32_LSTAR MSR
Problem: In response to an INIT reset initiated either via the INIT# pin or an IPI (Inter Processor
Interrupt), the processor should leave MSR values unchanged. Due to this erratum
IA32_LSTAR MSR (C0000082H), which is used by the iA32e SYSCALL instruction, is
being cleared by an INIT reset.
Implication: If software programs a value in IA32_LSTAR to be used by the SYSCALL instruction and
the processor subsequently receives an INIT reset, the SYSCALL instructions will not
behave as intended. Intel has not observed this erratum in any commercially available
software.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAA72. The XRSTOR Instruction May Fail to Cause a General-Protection
Exception
Problem: The XFEATURE_ENABLED_MASK register (XCR0) bits [63:9] are reserved and must be
0; consequently, the XRSTOR instruction should cause a general-protection exception if
any of the corresponding bits in the XSTATE_BV field in the header of the XSAVE/
XRSTOR area is set to 1. Due to this erratum, a logical processor may fail to cause such
an exception if one or more of these reserved bits are set to 1.
Implication: Software may not operate correctly if it relies on the XRSTOR instruction to cause a
general-protection exception when any of the bits [63:9] in the XSTATE_BV field in the
header of the XSAVE/XRSTOR area is set to 1.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
Intel® Xeon® Processor 3300 Series
Specification Update January 2012
37