Intel X3330 - Xeon 2.66 Ghz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor Specification page 31

Implication: This erratum may lead to livelock, shutdown or other unexpected processor behavior.
Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAA49. RSM Instruction Execution under Certain Conditions May Cause
Processor Hang or Unexpected Instruction Execution Results
Problem: RSM instruction execution, under certain conditions triggered by a complex sequence of
internal processor micro-architectural events, may lead to processor hang, or
unexpected instruction execution results.
Implication: In the above sequence, the processor may live lock or hang, or RSM instruction may
restart the interrupted processor context through a nondeterministic EIP offset in the
code segment, resulting in unexpected instruction execution, unexpected exceptions or
system hang. Intel has not observed this erratum with any commercially available
software.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAA50. Benign Exception after a Double Fault May Not Cause a Triple Fault
Shutdown
Problem: According to the Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 3A, "Exception and Interrupt Reference", if another exception occurs while
attempting to call the double-fault handler, the processor enters shutdown mode.
However due to this erratum, only Contributory Exceptions and Page Faults will cause a
triple fault shutdown, whereas a benign exception may not.
Implication: If a benign exception occurs while attempting to call the double-fault handler, the
processor may hang or may handle the benign exception. Intel has not observed this
erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAA51. LER MSRs May be Incorrectly UpdatedThe LER (Last Exception Record)
MSRs, MSR_LER_FROM_LIP (1DDH) and MSR_LER_TO_LIP (1DEH)
may contain incorrect values after any of the following:
• Either STPCLK#, NMI (NonMaskable Interrupt) or external interrupts
• CMP or TEST instructions with an uncacheable memory operand followed by a
conditional jump
• STI/POP SS/MOV SS instructions followed by CMP or TEST instructions and then by
a conditional jump
Implication: When the conditions for this erratum occur, the value of the LER MSRs may be
incorrectly updated.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAA52. Short Nested Loops That Span Multiple 16-Byte Boundaries May Cause
a Machine Check Exception or a System Hang
Problem: Under a rare set of timing conditions and address alignment of instructions in a short
nested loop sequence, software that contains multiple conditional jump instructions
Intel® Xeon® Processor 3300 Series
Specification Update January 2012
31