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wide range (2 Kbps to 2 Mbps). The PECI interface on the processor is disabled by
default and must be enabled through BIOS. More information can be found in the
Platform Environment Control Interface (PECI) Specification.
5.3.1.1
T
CONTROL
Fan speed control solutions based on PECI utilize a T
processor IA32_TEMPERATURE_TARGET MSR. The T
temperature format as PECI though it contains no sign bit. Thermal management
devices should infer the T
should utilize the relative temperature value delivered over PECI in conjunction with the
T
CONTROL
fan control diagram using PECI temperatures.
The relative temperature value reported over PECI represents the delta below the onset
of thermal control circuit (TCC) activation as indicated by PROCHOT# assertions. As the
temperature approaches TCC activation, the PECI value approaches zero. TCC activates
at a PECI count of zero.
Figure 16.
Conceptual Fan Control Diagram on PECI-Based Platforms
5.3.2
PECI Specifications
5.3.2.1
PECI Device Address
The PECI register resides at address 30h.
5.3.2.2
PECI Command Support
PECI command support is covered in detail in the Platform Environment Control
Interface Specification. Refer to this document for details on supported PECI command
function and codes.
82
and TCC activation on PECI-Based Systems
CONTROL
MSR value to control or optimize fan speeds.
Thermal Specifications and Design Considerations
CONTROL
CONTROL
value as negative. Thermal management algorithms
Figure 16
value stored in the
MSR uses the same offset
shows a conceptual
Datasheet
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