Intel BX80571E5300 - Pentium 2.6 GHz Processor Datasheet page 56

Table 23.
Land # Land Name
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23 RESERVED
F24
F25
F26
F27
F28
F29 RESERVED
G1
G2
TESTHI8/
G3
TESTHI9/
G4
G5
G6 RESERVED
G7
G8
G9
G10
G11
G12 DSTBN1#
G13
G14
G15
G16
G17
G18
G19 DSTBP2#
56
Numerical Land
Assignment
Signal Buffer
Type
D23# Source Synch Input/Output
D24# Source Synch Input/Output
VSS Power/Other
D28# Source Synch Input/Output
D30# Source Synch Input/Output
VSS Power/Other
D37# Source Synch Input/Output
D38# Source Synch Input/Output
VSS Power/Other
D41# Source Synch Input/Output
D43# Source Synch Input/Output
VSS Power/Other
TESTHI7 Power/Other
TESTHI2 Power/Other
TESTHI0 Power/Other
VTT_SEL Power/Other
BCLK0 Clock
FC27 Power/Other
COMP2 Power/Other
Power/Other
FC42
Power/Other
FC43
PECI Power/Other Input/Output
DEFER# Common Clock
BPRI# Common Clock
D16# Source Synch Input/Output
FC38 Power/Other
DBI1# Source Synch Input/Output
Source Synch Input/Output
D27# Source Synch Input/Output
D29# Source Synch Input/Output
D31# Source Synch Input/Output
D32# Source Synch Input/Output
D36# Source Synch Input/Output
D35# Source Synch Input/Output
Source Synch Input/Output
Table 23.
Direction Land # Land Name
G20 DSTBN2#
G21 D44#
G22 D47#
G23 RESET#
G24 TESTHI6
G25 TESTHI3
G26 TESTHI5
G27 TESTHI4
G28 BCLK1
G29 BSEL0
G30 BSEL2
H1 GTLREF0
H2 GTLREF1
Input H3
Input H4
Input H5 TESTHI10
Output H6
Input H7
H8
H9
Input H10
H11
Input
H12
Input
H13
H14
H15
H16
Input
H17
Input
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
Land Listing and Signal Descriptions
Numerical Land
Assignment
Signal Buffer
Direction
Type
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Common Clock
Power/Other
Power/Other
Power/Other
Power/Other
Clock
Asynch CMOS
Asynch CMOS
Power/Other
Power/Other
VSS Power/Other
FC35 Power/Other
Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
FC32 Power/Other
FC33 Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
Input
Input
Input
Input
Input
Input
Output
Output
Input
Input
Input
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