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2.2.3
FSB Decoupling
The processor integrates signal termination on the die. In addition, some of the high
frequency capacitance required for the FSB is included on the processor package.
However, additional high frequency capacitance must be added to the motherboard to
properly decouple the return currents from the front side bus. Bulk decoupling must
also be provided by the motherboard for proper [A]GTL+ bus operation.
2.3
Voltage Identification
The Voltage Identification (VID) specification for the processor is defined by the Voltage
Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop
LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage
to be delivered to the processor VCC lands (see
specifications). Refer to
for each processor frequency is provided in
Note:
To support the Deeper Sleep State the platform must use a VRD 11.1 compliant
solution. The Deeper Sleep State also requires additional platform support.
Individual processor VID values may be calibrated during manufacturing such that two
devices at the same core speed may have different default VID settings. This is
reflected by the VID Range values provided in
dual-core Processor E5000 Series Specification Update for further details on specific
valid core frequency and VID values of the processor. Note that this differs from the
VID employed by the processor during a power management event (Thermal Monitor 2,
Enhanced Intel SpeedStep
The processor uses eight voltage identification signals, VID[7:0], to support automatic
selection of power supply voltages.
the state of VID[7:0]. A '1' in this table refers to a high voltage level and a '0' refers to
a low voltage level. If the processor socket is empty (VID[7:0] = 11111110), or the
voltage regulation circuit cannot supply the voltage that is requested, it must disable
itself.
The processor provides the ability to operate while transitioning to an adjacent VID and
its associated processor core voltage (V
line. It should be noted that a low-to-high or high-to-low voltage state change may
result in as many VID transitions as necessary to reach the target core voltage.
Transitions above the specified VID are not permitted.
and DC shift ranges. Minimum and maximum voltages must be maintained as shown in
Table
5, and
The VRM or VRD utilized must be capable of regulating its output to the value defined
by the new VID. DC specifications for dynamic VID transitions are included in
and
Table 5
14
Table 12
for the DC specifications for these signals. Voltages
®
technology, or Extended HALT State).
Figure
1, as measured across the VCC_SENSE and VSS_SENSE lands.
. Refer to the Voltage Regulator Design Guide for further details.
Chapter 2.6.3
Table
4.
Table
4. Refer to the Intel
Table 2
specifies the voltage level corresponding to
). This will represent a DC shift in the load
CC
Table 4
Electrical Specifications
for V
overshoot
CC
®
®
Pentium
includes VID step sizes
Table 4
Datasheet
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