Processor 7/7 - EUROCOM W860CU Service Manual

Processor 7/7

PCI-Express Configuration Sele ct
1 : Single PEG
CFG0
0 : Bifurcation enable
CF G0 R394 *3.01 K_1 % _04
CFG3 - PCI-Express Static Lane Reversal
1 : Normal Operation
CFG3
0 : Lane Numbers Reversed
15 -> 0, 14 -> 1, ...
CF G3
R389 *3.01 K_1 % _04
CFG4 - Display Port Presence
1 : Di sab lle d; No ph ys ica l D isp la y P ort
at tac hed to E mbe dde d Dis pla y P or t
CFG4
0 : En abl ed; A n e xte rn al Dis pla y Por t
d ev ice is co nn ect ed to th e E mbe dd ed
i sp lay Po rt
CF G4 R393 *3.01 K_1 % _04
CFG7 - Reserved - Temporarily used for
early Clarksfield samples.
C la rks fie ld (o nly fo r ear ly sam pl es
p re -ES 1) - C on nec t t o GND wi th 3. 01K
O hm /5% re sis to r
CFG7
N ot e: Onl y t em por ary f or ear ly CF D
s am ple s ( rPG A/ BGA ) [ Fo r d eta ils
p le ase re fer t o t he WW 33 MoW an d
s ig hti ng rep or t].
F or a com mon m oth erb oa rd des ign ( for
A UB an d C FD) , the pu ll -do wn res is tor
s ho uld be us ed . D oes n ot imp act A UB
f un cti ona lit y.
C F G7 R 390 * 3.01K _1% _04
CF G7
Cl ar ksf iel d (on ly fo r e ar ly sa mpl es
pr e- ES1 ) - C onn ec t t o G ND wi th 3. 01K O hm/ 5%
re si sto r
PROCESSOR 7/7 ( RESERVED )
R 319 * 0_04
D03C U3 4E
Q36
AO 3402L
D S V RE F _CH _A _DIM M
9 M VR E F_D Q_D IM 0
A P 25
R SV D1
R 563 AL 25
R SV D2
AL 24
R SV D3
10 0K_ 04 AL 22
3 DR A M RS T _C NT R L R SV D4
AJ 33
R SV D5
C 694 AG 9
R SV D6
M 27
R SV D7
47n_1 0V_ X 7R_04 L 28
R SV D8
J 17
R SV D9
H 17
R SV D1 0
D04 add C694,C695 G 25
R SV D1 1
R 326 *0_ 04 G 17
R SV D1 2
E 31
R SV D1 3
Q37 E 30
R SV D1 4
AO 3402L
D S V RE F _CH _B _DIM M
10 M VR E F_D Q_D IM 1
R 564
10 0K_ 04
3 DR A M RS T _C NT R L CF G0
A M 30
C FG [0]
C 695 A M 28
C FG [1]
A P 31
C FG [2]
47n_1 0V_ X 7R_04 CF G3 AL 32
C FG [3]
CF G4 AL 30
C FG [4]
A M 31
C FG [5]
A N 29
C FG [6]
CF G7 A M 32
C FG [7]
A K 32
C FG [8]
A K 31
C FG [9]
A K 28
C FG [10]
AJ 28
C FG [11]
A N 30
C FG [12]
A N 32
C FG [13]
AJ 32
C FG [14]
AJ 29
C FG [15]
AJ 30
C FG [16]
A K 30
C FG [17]
R 130 * 0_04 RS V D86 H 16
R SV D_ T P_ 86
RSVD86
Connect
to GND
B 19
R SV D1 5
A 19
R SV D1 6
R42 8 *0_04 H_R S VD 17_R A 20
R SV D1 7
R42 7 *0_04 H_R S VD 18_R B 20
R SV D1 8
D03
U 9
R SV D1 9
T 9
R SV D2 0
AC 9
R SV D2 1
A B 9
R SV D2 2
C 1
R SV D_ NCT F _23
A 3
R SV D_ NCT F _24
J 29
R SV D2 6
J 28
R SV D2 7
A 34
R SV D_ NCT F _28
A 33
R SV D_ NCT F _29
C 35
R SV D_ NCT F _30
B 35
R SV D_ NCT F _31
M O LE X 4798901 42
A J13
RS V D32
A J12
RS V D33
A H25
RS V D34
A K2 6
RS V D35
A L26
RS V D36
A R2
R SV D_ NCT F _37
A J26
RS V D38
A J27
RS V D39
A P1
R SV D_ NCT F _40
A T 2
R SV D_ NCT F _41
A T 3
R SV D_ NCT F _42
A R1
R SV D_ NCT F _43
A L28
RS V D45
A L29
RS V D46
A P3 0
RS V D47
A P3 2
RS V D48
A L27
RS V D49
A T 31
RS V D50
A T 32
RS V D51
A P3 3
RS V D52
A R33
RS V D53
A T 33
R SV D_ NCT F _54
A T 34
R SV D_ NCT F _55
A P3 5
R SV D_ NCT F _56
A R35
R SV D_ NCT F _57
A R32
RS V D58
E 15
RS V D_T P _59
F 15
RS V D_T P _60
A 2
KE Y
D15
RS V D62
C15
RS V D63
A J15 RS V D64 _R R 127 *0 _04
RS V D64 RS V D65 _R
A H15 R 138 *0 _04
RS V D65
A A5
RS V D_T P _66
A A4
RS V D_T P _67
R8
RS V D_T P _68
A D3
RS V D_T P _69
A D2
RS V D_T P _70
A A2
RS V D_T P _71
A A1
RS V D_T P _72
R9
RS V D_T P _73
A G7
RS V D_T P _74
A E3
RS V D_T P _75
V 4
RS V D_T P _76
V 5
RS V D_T P _77
N2
RS V D_T P _78
A D5
RS V D_T P _79
A D7
RS V D_T P _80
W 3
RS V D_T P _81
W 2
RS V D_T P _82
N3
RS V D_T P _83
A E5
RS V D_T P _84
A D9
RS V D_T P _85
A P3 4 T P _RS V D86 VSS (AP34) can be left NC is
V S S
CRB implementation ; EDS/DG
recommendation to GND
Schematic Diagrams
Sheet 8 of 57
Processor 7/7
Processor 7/7 B - 9