Schematic Diagrams
Processor 2/7
Sheet 3 of 57
Processor 2/7
B - 4 Processor 2/7
PROCESSOR
Processor Compensation Signals
H _ C O MP 3
H _ C OM P 0
H _ C O MP 2
R 4 04
4 9. 9_ 1 % _0 4
R 1 32
4 9. 9_ 1 % _0 4
H _ C OM P 1
H _ C O MP 1
H _ C O MP 0
R 4 11
2 0_ 1 % _ 04
H _ C OM P 2
R 4 13
2 0_ 1 % _ 04
H _ C OM P 3
H _ C A T E R R #
R 5 3 7
1 6 , 25
H _ P E C I
D03 ADD
R537
Processor Pullups
R 11 0
0 _0 4
H _ P R O C H OT # _ D
3 9
H _ P R OC H O T#
If P ROCH OT# is no t us ed, then it must be t ermi nate d
with a 5 0-O pull- up r esis tor to V TT_1 .1 ra il.
1 . 1 V S _ V T T
1 6
H _T H R MT R I P #
R 4 25
4 9. 9_ 1 % _0 4
H _ C A TE R R #
R 1 09
6 8_ 0 4
H _ P R OC H OT # _ D
FO R XD P
R 4 08
*6 8 _ 04
H _ C P U R S T#
R 40 7
*1 K _ 0 4
H _C P U R S T #
1 5 , 2 4 , 28 , 4 1
P L T_ R S T #
1 3
H _ P M_ S Y N C
R 1 3 5
* 0_ 0 4
S Y S _ A G E N T _ P W R O K
1 3 , 39
D E L A Y _ P W R GD
R 4 4 9
0 _ 04
16
H _ C P U P W R G D
C 6 85
0 . 1u _ 1 0V _X 7 R _ 0 4
R 4 3 2
0 _ 04
V D D P W R G OO D _ R
13
P M _ D R A M_ P W R GD
C 6 86
0 . 1u _ 1 0V _X 7 R _ 0 4
1 3
H _ V T T P W R G D
C onne ct to the Pro cess or ( VTTP WRGOO D) V TT_1 .1 V R po wer
g ood signa l to pro cess or. Sign al vo ltag e le vel is 1 .1
H _ P W R GD _ X D P
V .
C 6 87
0 . 1u _ 1 0V _X 7 R _ 0 4
R 1 3 1
1 . 5 K _ 1% _ 0 4
P LT _ R S T# _ R
1 2 , 15 , 2 5 , 2 6, 2 7 , 2 9
B U F _ P L T _R S T #
Sign al fr om P CH t o Pr oces sor
Conn ect t o PC H (P LT_R ST#)
R 1 2 5
(nee ds to be leve l tr ansl ated
D03 ADD
7 50 _ 1 %_ 0 4
from 3.3 V to 1.1 V).
C685 ,C686,C687
1. 5V
+ 1 . 5 S _ C P U
D03C add R554
D R A MP W R G D _ C P U
R 5 6 6
R 1 1 5
R 5 5 4
*1 . 1 K _ 1% _ 0 4
*1 . 1 K _ 1 %_ 0 4
1. 5 K _ 1 % _0 4
D D R 3 _D R A M R S T#
9, 1 0
D D R 3 _ D R A M R S T #
V D D P W R G OO D _ R
D04 add R5 66
R 1 2 1
7 50 _ 1 % _0 4
1 6
D R A M R S T _ C N TR L _P C H
8
D R A M R S T _ C N TR L
D0 3C R12 1 cha nge 75 0 ohm , R115 NC
2/7
( CLK,MISC,JTAG )
U 3 4 B
A T 23
C OM P 3
A 1 6
B C LK
B C L K _C P U _ P 1 6
A T 24
B 1 6
B C L K _C P U _ N
C OM P 2
B C L K #
G 16
A R 3 0
B C LK _I T P _ P
C OM P 1
B C L K _ I TP
A T 30
B C LK _I T P _ N
B C L K _ I T P #
A T 26
C OM P 0
E 1 6
C LK _E X P _ P 1 2
P E G_ C LK
D 1 6
C LK _E X P _ N
A H 24
P E G _C L K #
S K TO C C #
A 1 8
R 5 48
0 _ 04
D P L L _ R E F _ S S C LK
A 1 7
R 5 49
0 _ 04
A K 14
D P L L _ R E F _ S S C L K #
C A T E R R #
D03 A DD R548,R54 9 & DE L
CLK_D P_N/P
F 6
C P U _ D R A M R S T #
S M_ D R A MR S T #
0 _ 0 4
A T 15
P E C I
S M _R C O MP _ 0
A L 1
D0 3C
S M _ R C OM P [ 0]
A M1
S M _R C O MP _ 1
S M _ R C OM P [ 1]
S M _R C O MP _ 2
A N 1
A N 26
S M _ R C OM P [ 2]
P R OC H O T #
P M _E XT T S # [ 0 ]
A N 1 5
P M _ E X T_ T S # [ 0]
A P 1 5
P M _E XT T S # [ 1 ]
P M _ E X T_ T S # [ 1]
A K 15
T H E R M TR I P #
A T 28
X D P _ P R D Y #
P R D Y #
A P 2 7
X D P _ P R E Q#
P R E Q #
X D P _ T C L K
A N 2 8
A P 26
T C K
A P 2 8
X D P _ T MS
R E S E T _ OB S #
T MS
X D P _ T R S T#
A T 27
TR S T #
X D P _ T D I _ R
A L 15
A T 29
P M_ S Y N C
T D I
A R 2 7
X D P _ T D O _ R
T D O
A R 2 9
X D P _ T D I _ M
3 . 3 V S
T D I _ M
A N 14
A P 2 9
X D P _ T D O _ M
V C C P W R G OO D _ 1
TD O_ M
A N 2 5
H _D B R # _ R
R 4 1 0
* 1K _ 0 4
D B R #
A N 27
V C C P W R G OO D _ 0
A J 22
X D P _ O B S 0 _R
B P M # [ 0]
A K 13
A K 2 2
X D P _ O B S 1 _R
S M_ D R A MP W R OK
B P M # [ 1]
A K 2 4
X D P _ O B S 2 _R
B P M # [ 2]
A J 24
X D P _ O B S 3 _R
B P M # [ 3]
A M 15
A J 25
X D P _ O B S 4 _R
V TT P W R GO OD
B P M # [ 4]
A H 2 2
X D P _ O B S 5 _R
B P M # [ 5]
A K 2 3
X D P _ O B S 6 _R
B P M # [ 6]
X D P _ O B S 7 _R
A M 26
A H 2 3
T A P P W R G OO D
B P M # [ 7]
A L 14
R S T I N #
X D P _ T D O _ M
X D P _ T D I _ M
R 5 1 4
* 10 m i l _ s h or t
MO LE X 4 7 9 89 0 1 42
1 . 5 V
D03C
1 3 , 36
1 . 1 V S _ P W R GD
R 5 5 5
1 K _ 04
R 5 56
* 0 _0 4
3 . 3 V
Q3 4
MT N 70 0 2 Z H S 3
D
S
C P U _ D R A MR S T #
R 55 8
1 0 K _ 04
+ 1. 5S _ C P U
R 5 59
G
R 5 6 0
0 _ 04
1 0 0 K _ 04
B
Q 39
2 N 3 9 0 4
C 6 9 1
4 7 n_ 1 0 V _ X7 R _0 4
3 . 3V
2 , 1 1, 1 2 , 1 3, 15 , 1 6 , 18 , 2 1 , 2 4, 2 6 , 2 7 , 28 , 2 9 , 34 , 3 6 , 3 7, 3 8 , 4 1
3 . 3V S
9 , 1 0, 1 1 , 1 2, 13 , 1 5 , 16 , 1 7 , 1 8, 2 0 , 2 1 , 22 , 2 3 , 24 , 2 5 , 2 6, 2 7 , 2 8 , 29 , 3 0 , 3 1, 3 2 , 3 3, 34 , 3 9
1 . 1V S _V TT 5 , 6 , 1 6, 1 7 , 1 8 , 38
1 . 5V
9 , 1 0, 1 8 , 2 8, 34 , 3 7 , 41
+ 1. 5 S _ C P U 6 , 3 4
DDR3 Compensation Signals
1 6
S M_ R C OM P _ 0
R 49 3
1 00 _ 1 %_ 0 4
S M_ R C OM P _ 1
R 49 0
2 4. 9 _ 1 % _0 4
12
S M_ R C OM P _ 2
R 48 7
1 30 _ 1 %_ 0 4
1 . 1 V S _ V T T
R 1 4 6
10 K _ 0 4
R 4 3 9
10 K _ 0 4
R 4 4 3
0 _ 04
P M_ E X T T S #_ E C
2 5
R 1 4 1
0 _ 04
T S #_ D I MM 0_ 1 9 , 1 0
R 4 5 3
*1 2 . 4K _ 1 % _ 04
1 . 1 V S _ V T T
X D P _T M S
R 39 9
* 51 _ 0 4
X D P _T D O_ M
R 39 8
5 1 _ 04
X D P _T D I _R
R 39 7
* 51 _ 0 4
X D P _P R E Q #
R 40 3
* 51 _ 0 4
X D P _T C LK
R 40 0
* 51 _ 0 4
X D P _T R S T#
R 40 2
5 1 _ 04
3 . 3 V
C 69 0
0. 1u _ 1 0V _ X 7 R _ 0 4
U 3 8
74 A H C 1 G0 8 GW
1
D R A M P W R G D _ C P U
4
2
3 . 3 V
R 5 5 3
1 0K _ 0 4
+ 1 . 5 S _ C P U _P W R G D 3 7
Q3 8
MT N 70 0 2 Z H S 3
D03C
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