Dell Broadcom NetXtreme Family of Adapters User Manual page 126

Control
A2
Register
A3 Interrupt
Built-In Self-
A4
Test
PCI Cfg
A5
Register
Group B: Memory Tests
B1 Scratch Pad
B2 BD SRAM
B3 DMA SRAM
B4 MBUF SRAM
MBUF SRAM
B5
via DMA
B7 CPU GPR
Group C: Miscellaneous Tests
C1 NVRAM
C2 CPU
incrementing test data.
Each register specified in the configuration content defines the read-only bit and the read/write bits.
The test writes 0s and 1s to the test bits to ensure the read-only bits are not changed, and that
read/write bits are changed.
This test attempts to read the register configuration file (Ctrlreg.txt) for the register definitions. If
the file does not exist, a default register offset and mask bits are used.
Offset Read-Only Mask
0x00000400 0x00000000
0x00000404 0x03800107
This test verifies the interrupt functionality. It enables an interrupt and waits 500 ms for the
interrupt to occur and reports an error if it cannot generate the interrupt.
This is the hardware built-in self-test (BIST).
This test verifies the access integrity of the PCI configuration registers.
This test tests the onboard scratchpad SRAM. The following tests are performed:
Address Test. This test writes each address with a unique increment of data and reads back data
to ensure data is correct. After filling the entire address with the unique data, the program reads
back the data again to ensure that the data is still correct.
Walking bit. For each address, data one is written and read back for testing. Then it shifts the
data left one bit, so the data becomes two and repeats the same test. It repeats the test 32 times
until the test bit is shifted out of the test address. The same test is repeated for entire test range.
Pseudo-Random Data. A precalculated pseudo-random data set is used to write unique data to
each test RAM. After passing the test, the program reads back the data one more time to ensure
that the data is still correct.
Data Read/Write Test: This test writes test data to the SRAM and reads it back to ensure that
the data is correct. The test data used is 0x00000000, 0xFFFFFFFF, 0xAA55AA55, and 0x55AA55AA.
Alternate Data Pattern Test. This test writes test data into the SRAM, writes complement test
data to the next address, and reads back both to ensure the data is correct. After the test, the
program reads back data one more time to ensure that the data is still correct. The test data used
is 0x00000000, 0xFFFFFFFF, 0xAA55AA55, and 0x55AA55AA.
This test tests the Buffer Descriptor (BD) SRAM. This test performs in the same way as the Scratch
Pad Test described in B1.
This test tests the direct memory access (DMA) SRAM by performing the Scratch Pad Test described
in test B1.
This test tests the memory access buffer (MBUF) SRAM by performing the Scratch Pad Test
described in test B1.
This test uses 8 data test patterns. A 0x1000-sized data buffer is used for this test. Before each
pattern test, the buffer is initialized and filled with the test pattern. It then performs a 0x1000-sized
transmit DMA from the host buffer to the adapter MBUF memory.
The test verifies the data integrity in the adapter MBUF memory against the host memory and
repeats the DMA for the entire MBUF buffer. Then, the test performs a receive DMA from the
adapter to the host. The 0x1000-byte test buffer is cleared to 0 before each receive DMA. After the
test verifies the integrity of the data, the test is repeated for the entire MBUF SRAM range. The 8
test patterns are described below.
Test Pattern Description
16 00s and 16 FF's Fills the entire host DMA buffer with 16 bytes of 00s and then
16 bytes of FF's.
16 FF's and 16 00s Fills the entire host DMA buffer with 16 bytes of FF's and then
16 bytes of 00s.
32 00s and 32 FF's Fills the entire host DMA buffer with 32 bytes of 00s and then
32 bytes of FF's.
32 FF's and 32 00s Fills the entire host DMA buffer with 32 bytes of FF's and then
32 bytes of 00s.
00000000 Fills the entire host DMA buffer with all 00s.
FFFFFFFF Fills the entire host DMA buffer with all FF's.
AA55AA55 Fills the entire host DMA buffer with data 0xAA55AA55.
55AA55AA Fills the entire host DMA buffer with data 0x55AA55AA.
This test tests the CPU General Purpose registers and performs in the same way as the Scratch Pad
Test (B1) over 3 different voltages (1.1V, 1.2V, and 1.3V).
Incremental test data is used in the electrically erasable programmable read-only memory
(EEPROM) test. The test fills the test range with test data and reads the data back to verify the
content. Afterwards, the test fills the test range with 0s to clear the memory.
This test opens the Cpu.bin file. If the file exists and content is good, the test loads code to the RX
CPU and TX CPU and verifies the CPU execution.
Read/Write Mask
0x007FFF8C
0x00000000