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5.2 Intel ICH6-M South Bridge(10)
Functional Strap Definitions 1
Signal
Usage
When Sampled
GNT[6]#/
Top-Block Swap
Rising Edge of
GPO[16]
Override
PWROK
LINKALERT
Reserved
#
SPKR
No Reboot
Rising Edge
ofPWROK
INTVRMEN IntegratedVccSu
Always
1_5VRM
Enable/Disable
GPIO[25]
Integrated
Rising Edge of
Vcc2_5 VRM
RSMRST#
Enable/ Disable
EE_CS
Reserved
GNT[5]#/
Boot BIOS
Rising Edge of
GPO[17]
Destination
PWROK
Selection
80
50QMA
N/B Maintenance
80
50QMA
Description
The signal has a weak internal pull-up. If the
signal is sampled low, this indicates that the
system is strapped to the "top-block swap" mode
(ICH6 inverts A16 for all cycles targeting FWH
BIOS space). The status of this strap is readable
via the Top Swap bit (Chipset Configuration
Registers:Offset 3414h:bit 0). Note that software
will not be able to clear the Top-Swap bit until
the system is rebooted without GNT6# being
pulled down.
This signal requires an external pull-up resistor.
The signal has a weak internal pull-down. If the
signal is.sampled high, this indicates that the
system is strapped to.the "No Reboot" mode
(ICH6 will disable the TCO Timer. system
reboot feature). The status of this strap is
readable. via the NO REBOOT bit (Chipset
Configuration. Registers:Offset 3410h:bit 5).
This signal enables integrated VccSus1_5 VRM
when.sampled high.
This signal enables integrated Vcc2_5 VRM
when sampled low. This signal has a weak
internal pull-up during RSMRST# and is
disabled within 100 ms after RSMRST#
de-asserts.
This signal has a weak internal pull-down.
NOTE: This signal should not be pulled high.
This signal has a weak internal pull-up. Allows
for select memory ranges to be forwarded out the
PCI Interface as opposed to the Firmware Hub.
When sampled high, destination is LPC. Also
controllable via Boot BIOS Destination bit
(Chipset Configuration Registers:Offset
3410h:bit 3).
NOTE: This functionality intended for
debug/testing only.
N/B Maintenance
Functional Strap Definitions 1 (Continued)
Signal
Usage
EE_DOUT
Reserved
ACZ_SDOU
XOR Chain
T
Entrance / PCI
Express* Port
Configu-ration
bit 1
ACZ_SYNC
PCI Express Por
Configu-ration
bit 0
TP[1]
Reserved
SATALED#
Reserved
REQ[4:1]#
XOR Chain
Selection
TP[3]
XOR Chain
Entrance
Real Time Clock Interface
Name
Type
Special Crystal Input 1: This signal is connected to the 32.768 kHz crystal.
RTCX1
Special Crystal Input 2: This signal is connected to the 32.768 kHz crystal.
RTCX2
When Sampled
Description
This signal has a weak internal pull-up.
NOTE: This signal should not be pulled low.
Rising Edge of
Allows entrance to XOR Chain testing when
PWROK
TP[3] pulled low at rising edge of PWROK. See
Chapter 24 for XOR Chain functionality
information.
When TP[3] not pulled low at rising edge of
PWROK, sets bit 1 of RPC.PC (Chipset
Configuration Registers:Offset 224h). See
Section 7.1.30 for details.
This signal has a weak internal pull-down.
Rising Edge of
This signal has a weak internal pull-down.
PWROK
Sets bit 0 of RPC.PC (Chipset Configuration
Registers: Off set 224h). See Section 7.1.30 for
details.
This signal has a weak internal pull-down.
NOTE: This signal should not be pulled high.
This signal has a weak internal pull-up enabled
only when PLTRST# is asserted.
NOTE: This signal should not be pulled low.
Rising Edge of
See Chapter 24 for functionality information.
PWROK
Rising Edge of
See Chapter 24 for functionality information.
PWROK
This signal has a weak internal pull-up.
NOTE: This signal should not be pulled low
unless using XOR Chain testing.
Description
If no external crystal is used, then RTCX1 can be driven with the
desired clock rate.
If no external crystal is used, then RTCX2 should be left floating.
97
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