Table of Contents
Advertisement
5.2 Intel ICH6-M South Bridge(2)
PCI Interface Signals (Continued)
Name
Type
Description
I/O
Parity Error: An external PCI device drives PERR# when it receives
PERR#
data that has a parity error. The ICH6 drives PERR# when it detects a
parity error. The ICH6 can either generate an NMI# or SMI# upon
detecting a parity error (either detected internally or reported via the
PERR# signal).
I
PCI Requests: The ICH6 supports up to 7 masters on the PCI bus.
REQ[0:3]#
REQ[4]# / GPI[40]
The REQ[4]#, REQ[5]#, and REQ[6]# pins can instead be used as a
REQ[5]# / GPI[1]
GPI.
REQ[6]# / GPI[0]
O
PCI Grants: The ICH6 supports up to 7 masters on the PCI bus. The
GNT[0:3]#
GNT[4]# pin can instead be used as a GPO.
GNT[4]# /
GPO[48]
Pull-up resistors are not required on these signals. If pull-ups are
used, they should be tied to the Vcc3_3 power rail.
GNT[5]# /
GPO[17]#
GNT[5]#/GPO[17] and GNT[6]#/GPO[17] both have an internal
pull-up.
GNT[6]# /
GPO[16]#
NOTE: GNT[6] is sampled at the rising edge of PWROK as a
functional strap. See Section 2.22.1 for more details. There is a weak,
integrated pull-up resistor on the GNT[6] pin.
I
PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all
PCICLK
transactions on the PCI Bus.
O
PCI Reset: This is the Secondary PCI Bus reset signal. It is a logical
PCIRST#
OR of the primary interface PLTRST# signal and the state of the
Secondary Bus Reset bit of the Bridge Control register (D30:F0:3Eh,
bit 6).
NOTE: PCIRST# is in the VccSus3_3 well.
I/O
PCI Lock: This signal indicates an exclusive bus operation and may
PLOCK#
require multiple transactions to complete. ICH6 asserts PLOCK#
when it performs non-exclusive transactions on the PCI bus.
PLOCK# is ignored when PCI masters are granted the bus.
OD I/O System Error: SERR# can be pulsed active by any PCI device that
SERR#
detects a system error condition. Upon sampling SERR# active, the
ICH6 has the ability to generate an NMI, SMI#, or interrupt.
OD I
PCI Power Management Event: PCI peripherals drive PME# to
PME#
wake the system from low-power states S1–S5. PME# assertion can
also be enabled to generate an SCI from the S0 state. In some cases
the ICH6 may drive PME# active due to an internal wake event. The
ICH6 will not drive PME# high, but it will be pulled up to VccSus3_3
by an internal pull-up resistor.
80
50QMA
N/B Maintenance
80
50QMA
N/B Maintenance
Serial ATA Interface Signals
Name
Type
Description
O
Serial ATA 0 Differential Transmit Pair: These are outbound
SATA[0]TXP
high-speed differential signals to Port 0.
SATA[0]TXN
I
Serial ATA 0 Differential Receive Pair: These are inbound
SATA[0]RXP
high-speed differential signals from Port 0.
SATA[0]RXN
O
Serial ATA 1 Differential Transmit Pair: These are outbound
SATA[1]TXP
high-speed differential signals to Port 1.
SATA[1]TXN
I
Serial ATA 1 Differential Receive Pair: These are inbound
SATA[1]RXP
high-speed differential signals from Port 1.
SATA[1]RXN
O
Serial ATA 2 Differential Transmit Pair: These are outbound
SATA[2]TXP
high-speed differential signals to Port 2.
SATA[2]TXN
I
Serial ATA 2 Differential Receive Pair: These are inbound
SATA[2]RXP
high-speed differential signals from Port 2.
SATA[2]RXN
O
Serial ATA 3 Differential Transmit Pair: These are outbound
SATA[3]TXP
high-speed differential signals to Port 3.
SATA[3]TXN
I
Serial ATA 3 Differential Receive Pair: These are inbound
SATA[3]RXP
high-speed differential signals from Port 3.
SATA[3]RXN
O
Serial ATA Resistor Bias: These are analog connection points for an
SATARBIAS
external resistor to ground.
I
Serial ATA Resistor Bias Complement: These are analog
SATARBIAS#
connection points for an external resistor to ground.
I
Serial ATA 0 General Purpose: This is an input pin which can be
SATA[0]GP /
configured as an interlock switch corresponding to SATA Port 0.
GPI[26]
When used as an interlock switch status indication, this signal should
be drive to '0' to indicate that the switch is closed and to '1' to
indicate that the switch is open.
If interlock switches are not required, this pin can be configured as
GPI[26].
NOTE: All SATAxGP pins must be configured with the same
function: as either SATAxGP pins or GPI pins.
I
Serial ATA 1 General Purpose: Same function as SATA[0]GP,
SATA[1]GP /
except for SATA Port 1.
GPI[29]
If interlock switches are not required, this pin can be configured as
GPI[29].
I
Serial ATA 2 General Purpose: Same function as SATA[0]GP,
SATA[2]GP /
except for SATA Port 2.
GPI[30]
If interlock switches are not required, this pin can be configured as
GPI[30].
89
Advertisement
Table of Contents
