MiTAC 8050QMA Service Manual page 26

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JEDEC standard 1.8V I/O (SSTL_18-compatible)
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Differential data strobe (DQS,DQS#) option
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Four-bit prefetch architecture
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Differential clock input (CK,CK#)
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Command entered on each rising CK edge
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DQS edge-aligned with data for Reads
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DQS center-aligned with data for Writes
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Duplicate output strobe (RDQS) option for x8 configuration
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DLL to align DQ and DQS transitions with CK
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Four internal banks for concurrent operation
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Data mask (DM) for masking write data
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Programmable CAS Latency (CL) : 2,3,4 and 5
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Posted CAS additive latency (AL) : 0,1,2,3 and 4
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Write latency = Read latency – 1
50QMA N/B Maintenance
50QMA N/B Maintenance
t CK
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