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5.1 Intel 915PM North Bridge(2)
Host Interface Signals (Continued)
Signal Name
Type
Description
HLOCK#
I
Host Lock:
AGTL+
All CPU bus cycles sampled with the assertion of HLOCK# and
HADS#, until the negation of HLOCK# must be atomic, i.e. PCI
Express graphics access to System Memory is allowed when
HLOCK# is asserted by the CPU.
HREQ[4:0]#
I/O
Host Request Command:
AGTL+
Defines the attributes of the request. HREQ[4:0]# are transferred at
2X
2x rate.
Asserted by the requesting agent during both halves of the Request
Phase. In the first half the signals define the transaction type to a level
of detail that is sufficient to begin a snoop request. In the second half
the signals carry additional information to define the complete
transaction type.
HTRDY#
O
Host Target Ready:
AGTL+
Indicates that the target of the processor transaction is able to enter
the data transfer phase.
HRS[2:0]#
O
Host Response Status:
AGTL+
Indicates the type of response according to the following the table:
HRS[2:0]#
000
001
010
011
100
101
110
111
HDPWR#
O
Host Data Power:
AGTL+
Used by GMCH to indicate that a data return cycle is pending within
2 HCLK cycles or more. CPU use's this signal during a read-cycle to
activate the data input buffers in preparation for HDRDY# and the
related data.
HCPUSLP#
O
Host CPU Sleep:
CMOS
When asserted in the Stop-Grant state, causes the processor to enter
the Sleep state. During Sleep state, the processor stops providing
internal clock signals to all units, leaving only the Phase-Locked
Loop (PLL) still operating. Processors in this state will not recognize
snoops or interrupts.
80
50QMA
80
50QMA
Response type
Idle state
Retry response
Deferred response
Reserved (not driven by GMCH)
Hard Failure (not driven by GMCH)
No data response
Implicit Write back
Normal data response
N/B Maintenance
N/B Maintenance
Host Interface Reference and Compensation
Signal Name
Type
HVREF
I
A
HXRCOMP
I/O
A
HXSCOMP
I/O
A
HXSWING
I
A
HYRCOMP
I/O
A
HYSCOMP
I/O
A
HYSWING
I
A
DMI
Signal Name
Type
DMI_RXP[1:0]
I
DMI_RXN[1:0]
PCIE
DMI_TXP[1:0]
O
DMI_TXN[1:0]
PCIE
DMI x2 is supported for Intel 915GMS chipset
Description
Host Reference Voltage:
Reference voltage input for the Data, Address, and Common clock
signals of the Host AGTL+ interface.
Host X RCOMP:
Used to calibrate the Host AGTL+ I/O buffers.
This signal is powered by the Host Interface termination rail (VCCP).
Host X SCOMP:
Slew Rate Compensation for the Host Interface
Host X Voltage Swing:
These signals provide reference voltages used by the HXRCOMP
circuits.
Host Y RCOMP:
Used to calibrate the Host AGTL+ I/O buffers.
Host Y SCOMP:
Slew Rate Compensation for the Host Interface
Host Y Voltage Swing:
These signals provide reference voltages used by the HYRCOMP
circuitry.
Description
DMI input from ICH6-M:
Direct Media Interface receive differential pair
DMI output to ICH6-M:
Direct Media Interface transmit differential pair
79
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