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5.2 Intel ICH6-M South Bridge(4)
IDE Interface Signals
Name
Type
Description
O
IDE Device Chip Selects for 100 Range: For ATA command
DCS1#
register block. This output signal is connected to the corresponding
signal on the IDE connector.
O
IDE Device Chip Select for 300 Range: For ATA control register
DCS3#
block. This output signal is connected to the corresponding signal on
the IDE connector.
O
IDE Device Address: These output signals are connected to the
DA[2:0]
corresponding signals on the IDE connector. They are used to indicate
which byte in either the ATA command block or control block is
being addressed.
I/O
IDE Device Data: These signals directly drive the corresponding
DD[15:0]
signals on the IDE connector. There is a weak internal pull-down
resistor on DD7.
I
IDE Device DMA Request: This input signal is directly driven from
DDREQ
the DRQ signal on the IDE connector. It is asserted by the IDE device
to request a data transfer, and used in conjunction with the PCI bus
master IDE function and are not associated with any AT compatible
DMA channel. There is a weak internal pull-down resistor on this
signal.
O
IDE Device DMA Acknowledge: This signal directly drives the
DDACK#
DAK# signal on the IDE connector. DDACK# is asserted by the Intel
ICH6 to indicate to IDE DMA slave devices that a given data transfer
cycle (assertion of DIOR# or DIOW#) is a DMA data transfer cycle.
This signal is used in conjunction with the PCI bus master IDE
function and are not associated with any AT-compatible DMA
channel.
DIOR# / (DWSTB
O
DIOR# /
/ RDMARDY#)
Disk I/O Read (PIO and Non-Ultra DMA): This is the command to
the IDE device that it may drive data onto the DD lines. Data is
latched by the ICH6 on the de-assertion edge of DIOR#. The IDE
device is selected either by the ATA register file
chip selects (DCS1# or DCS3#) and the DA lines, or the IDE DMA
acknowledge (DDAK#)
Disk Write Strobe (Ultra DMA Writes to Disk): This is the data write
strobe for writes to disk. When writing to disk, ICH6 drives valid data
on rising and falling edges of DWSTB.
Disk DMA Ready (Ultra DMA Reads from Disk): This is the DMA
ready for reads from disk. When reading from disk, ICH6 de-asserts
RDMARDY# to pause burst data transfers.
80
50QMA
N/B Maintenance
80
50QMA
N/B Maintenance
IDE Interface Signals (Continued)
Name
Type
Description
DIOW# / (DSTOP)
O
Disk I/O Write (PIO and Non-Ultra DMA): This is the command to
the IDE device that it may latch data from the DD lines. Data is
latched by the IDE device on the de-assertion edge of DIOW#. The
IDE device is selected either by the ATA register file chip selects
(DCS1# or DCS3#) and the DA lines, or the IDE DMA acknowledge
(DDAK#).
Disk Stop (Ultra DMA): ICH6 asserts this signal to terminate a burst.
IORDY / (DRSTB
I
I/O Channel Ready (PIO): This signal will keep the strobe active
/ WDMARDY#)
(DIOR# on reads, DIOW# on writes) longer than the minimum width.
It adds wait-states to PIO transfers.
Disk Read Strobe (Ultra DMA Reads from Disk): When reading from
disk, ICH6 latches data on rising and falling edges of this signal from
the disk.
Disk DMA Ready (Ultra DMA Writes to Disk): When writing to
disk, this is de-asserted by the disk to pause burst data transfers.
System Management Interface Signals
Name
Type
Description
I
Intruder Detect: This signal can be set to disable system if box
INTRUDER#
detected open.
This signal's status is readable, so it can be used like a GPI if the
Intruder Detection is not needed.
OD I/O System Management Link: SMBus link to optional external system
SMLINK[1:0]
management ASIC or LAN controller. External pull-ups are required.
Note that SMLINK0 corresponds to an SMBus Clock signal, and
SMLINK1 corresponds to an SMBus Data signal.
OD I/O SMLink Alert: Output of the integrated LAN and input to either the
LINKALERT#
integrated ASF or an external management controller in order for the
LAN's SMLINK slave to be serviced.
SM Bus Interface Signals
Name
Type
Description
OD I/O SMBus Data: External pull-up resistor is required.
SMBDATA
OD I/O SMBus Clock: External pull-up resistor is required.
SMBCLK
I
SMBus Alert: This signal is used to wake the system or generate
SMBALERT#/
GPI[11]
SMI#. If not used for SMBALERT#, it can be used as a GPI.
91
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