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5.2 Intel ICH6-M South Bridge(5)
USB Interface Signals
Name
Type
Description
I/O
Universal Serial Bus Port [1:0] Differential: These differential pairs
USBP[0]P,
are used to transmit Data/Address/Command signals for ports 0 and 1.
USBP[0]N,
These ports can be routed to UHCI controller #1 or the EHCI
USBP[1]P,
controller.
USBP[1]N
NOTE: No external resistors are required on these signals. The ICH6
integrates 15 K Ω ? p ull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor
I/O
Universal Serial Bus Port [3:2] Differential: These differential pairs
USBP[2]P,
are used to transmit data/address/command signals for ports 2 and 3.
USBP[2]N,
These ports can be routed to UHCI controller #2 or the EHCI
USBP[3]P,
controller.
USBP[3]N
NOTE: No external resistors are required on these signals. The ICH6
integrates 15 K Ω ? p ull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor
I/O
Universal Serial Bus Port [5:4] Differential: These differential pairs
USBP[4]P,
are used to transmit Data/Address/Command signals for ports 4 and 5.
USBP[4]N,
These ports can be routed to UHCI controller #3 or the EHCI
USBP[5]P,
controller.
USBP[5]N
NOTE: No external resistors are required on these signals. The ICH6
integrates 15 K Ω ? p ull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor
I/O
Universal Serial Bus Port [7:6] Differential: These differential pairs
USBP[6]P,
are used to transmit Data/Address/Command signals for ports 6 and 7.
USBP[6]N,
These ports can be routed to UHCI controller #4 or the EHCI
USBP[7]P,
controller.
USBP[7]N
NOTE: No external resistors are required on these signals. The ICH6
integrates 15 K Ω ? p ull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor
I
Overcurrent Indicators: These signals set corresponding bits in the
OC[3:0]#
OC[4]# / GPI[9]
USB controllers to indicate that an overcurrent condition has
OC[5]# / GPI[10]
occurred.
OC[6]# / GPI[14]
OC[7:4]# may optionally be used as GPIs.
OC[7]# / GPI[15]
NOTE: OC[7:0]# are not 5 V tolerant.
O
USB Resistor Bias: Analog connection point for an external resistor.
USBRBIAS
Used to set transmit currents and internal load resistors.
I
USB Resistor Bias Complement: Analog connection point for an
USBRBIAS#
external resistor. Used to set transmit currents and internal load
resistors.
80
50QMA
N/B Maintenance
80
50QMA
N/B Maintenance
EEPROM Interface Signals
Name
Type
Description
O
EEPROM Shift Clock: This signal is the serial shift clock output to
EE_SHCLK
the EEPROM.
I
EEPROM Data In: This signal transfers data from the EEPROM to
EE_DIN
the Intel ® ICH6. This signal has an integrated pull-up resistor.
O
EEPROM Data Out: This signal transfers data from the ICH6 to the
EE_DOUT
EEPROM.
O
EEPROM Chip Select: This is the chip select signal to the
EE_CS
EEPROM.
Miscellaneous Signals
Name
Type
Description
I
Internal Voltage Regulator Enable: This signal enables the internal
INTVRMEN
1.5 V Suspend regulator when connected to VccRTC. When
connected to Vss, the internal regulator is disabled
O
Speaker: The SPKR signal is the output of counter 2 and is internally
SPKR
"ANDed" with Port 61h bit 1 to provide Speaker Data Enable. This
signal drives an external speaker driver device that in turn drives the
system speaker. Upon PLTRST#, its output state is 0.
NOTE: SPKR is sampled at the rising edge of PWROK as a
functional strap. See Section 2.22.1 for more details. There is a weak
integrated pull-down resistor on SPKR pin.
I
RTC Reset: When asserted, this signal resets register bits in the RTC
RTCRST#
well.
NOTES:
1.
Unless CMOS is being cleared (only to be done in the G3 power
state), the RTCRST# input must always be high when all other
RTC power planes are on.
In the case where the RTC battery is dead or missing on the
2.
platform, the RTCRST# pin must rise before the RSMRST# pin.
I
Test Point 0: This signal must have an external pull-up to
TP[0]
VccSus3_3.
O
Test Point 1: Route signal to a test point.
TP[1]
O
Test Point 2: Route signal to a test point.
TP[2]
I
Test Point 3: Route signal to a test point.
TP[3]
O
Test Point 4: Route signal to a test point.
TP[4]
92
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