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8.2 No Display-2
L31
120Z/100M
+3VS
L32
C80
120Z/100M
2.2µ
DREFCLK
R101
DREFCLK#
R100
P
4
DREFSSCLK
R99
DREFSSCLK#
R87
U710
R111
CLK_GMCH
CLK_GMCH#
R113
HCLK_MCH
R125
North Bridge
HCLK_MCH#
R124
GMCH
CFG1
R71
1K
R72
1K
CFG2
P
U715
18
PCICLK_CARD
CB712
P
U717
15
28
PCICLK_LAN
RTL8100CL
P
U14
24
31
PCICLK_FWH
SST49LF004A
P
U13
23
70
PCICLK_KBC
W83L950D
80
50QMA
N/B Maintenance
80
50QMA
N/B Maintenance
****** System Clock Check ******
+3VS_CLK
C78
2.2µ
47
14
33
46
15
33
8
33
17
33
18
12
33
31
52
30
33
P
55
9
41
33
54
40
33
24
U7
FS_B
16
25
53
26
FS_C
27
Clock
Generator
36
35
ICS954226
44
43
R94
33
5
49
R104
33
4
50
R105
33
3
9
R114
39
33
56
+3VS
R76
R103
10K
10K
To J714,J713
P
8
SMBDATA
SMBCLK
R131
12.1
CLK_PCI_STOP#
CLK_CPU_STOP#
R98
33
R97
33
R96
33
R95
33
R123
33
R122
33
R127
33
R126
33
C97
56P
X1
14.318MHz
C98
56P
R92
33
PCICLK_MINIPCI
R136
475
+3VS
+VDD3S
R206
R207
R142
Q14
R144
2.2K
2.2K
2N7002
10K
10K
G
S
SMB_DATA
D
G
Q13
2N7002
SMB_CLK
D
S
R93
33
PCICLK_ICH
R80
33
CLK_USB48
14M_ICH
STOP_PCI#
STOP_CPU#
CLK_ICH
CLK_ICH#
CLK_SATA
CLK_SATA#
CLK_ITP_CPU
CLK_ITP_CPU#
HCLK_CPU
HCLK_CPU#
HBSEL0
HBSEL1
FS_C
FS_B
FS_A
BCLK Frequency
H
L
H
100 MHz (Default)
L
L
H
133 MHz
R710
0
25
P
11
U709
South Bridge
ICH6-M
P
2
U711
CPU
DOTHAN
J716
P
20
113
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