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5.2 Intel ICH6-M South Bridge(8)
General Purpose I/O Signals 1,2
Name
Type
Tolerance Power Well Description
OD O
V_CPU_IO
`Core
GPO[49]
O
3.3 V
Core
GPO[48]
N/A
N/A
N/A
GPIO[47:42]
I
3.3 V
Core
GPI[41]
I
5 V
Core
GPI[40]
N/A
N/A
N/A
GPIO[39:35]
I/O
3.3 V
Core
GPIO[34:33]
I/O
3.3 V
Core
GPIO[32]
I
3.3 V
Core
GPI[31]
I
3.3 V
Core
GPI[30]
I
3.3 V
Core
GPI[29]
I/O
3.3 V
Resume
GPIO[28:27]
I
3.3 V
Core
GPI[26]
I/O
3.3 V
Resume
GPIO[25]
I/O
3.3 V
Resume
GPIO[24]
O
3.3 V
Core
GPO[23]
N/A
N/A
N/A
GPIO[22]
O
3.3 V
Core
GPO[21]
O
3.3 V
Core
GPO[20]
O
3.3 V
Core
GPO[19]
80
50QMA
N/B Maintenance
80
50QMA
This signal is fixed as output only and can
instead be used as CPUPWRGD.
This signal is fixed as output only and can
instead be used as GNT4#.
This signal is not implemented.
This signal is fixed as input only and can be used
instead as LDRQ1#.
This signal is fixed as input only and can be used
instead as REQ4#.
This signal is not implemented.
This signal can be input or output and is
unmultiplexed
This signal can be input or output.
This signal is fixed as input only and can instead
be used for SATA[3]GP.
This signal is fixed as input only and can instead
be used for SATA[2]GP.
This signal is fixed as input only and can instead
be used for SATA[1]GP.
This signal can be input or output and is
unmultiplexed.
This signal is fixed as input only and can instead
be used for SATA[0]GP.
This signal can be input or output and is
unmultiplexed. It is a strap for internal Vcc2_5
regulator. See Section 2.22.1.
This signal can be input or output and is
unmultiplexed.
This signal is fixed as output only.
This signal is not Implemented
This signal is fixed as output only and is
unmultiplexed
This signal is fixed as output only.
This signal is fixed as output only.
NOTE: GPO[19] may be programmed to blink
(controllable by GPO_BLINK (D31:F0:Offset
GPIOBASE+18h:bit 19)).
N/B Maintenance
General Purpose I/O Signals 1,2 (Continued)
Name
Type
Tolerance Power Well Description
O
3.3 V
GPO[18]
O
3.3 V
GPO[17]
O
3.3 V
GPO[16]
I
3.3 V
GPI[15:14]3
I
3.3 V
GPI[13]3
I
3.3 V
GPI[12]3
I
3.3 V
GPI[11]3
I
3.3 V
GPI[10:9]3
I
3.3 V
GPI[8]3
I
3.3 V
GPI[7]3
I
3.3 V
GPI[6]3
I
GPI[5:2]3
I
GPI[1:0]3
NOTES:
1.All inputs are sticky. The status bit remains set as long as the input was asserted for two
clocks.GPIs are sampled on PCI clocks in S0/S1. GPIs are sampled on RTC clocks in S3/S4/S5.
2.Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO
signals are not driven high into powered-down planes. Some ICH6 GPIOs may be connected to
pins on devices that exist in the core well. If these GPIOs are outputs, there is a danger that a
loss of core power (PWROK low) or a Power Button Override event will result in the Intel
ICH6 driving a pin to a logic 1 to another device that is powered down.
3.GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to either
an SMI# or an SCI, but not both.
Core
This signal is fixed as output only.
NOTE: GPO[18] will blink by default
immediately after reset (controllable by
GPO_BLINK (D31:F0:Offset
GPIOBASE+18h:bit 18)).
Core
This signal is fixed as output only and can be
used instead as PCI GNT[5]#.
Core
This signal is fixed as output only and can be
used instead as PCI GNT[6]#.
Resume
This signal is fixed as input only and can be used
instead as OC[7:6]#
Resume
This signal is fixed as input only and is
unmultiplexed.
Core
This signal is fixed as input only and is
unmultiplexed.
Resume
This signal is fixed as input only and can be used
instead as SMBALERT#.
Resume
This signal is fixed as input only and can be used
instead as OC[5:4]#.
Resume
This signal is fixed as input only and is
unmultiplexed.
Core
This signal is fixed as input only and is
unmultiplexed.
Core
This signal is fixed as input only.
5 V
Core
This signal is fixed as input only and can be used
instead as PIRQ[H:E]#.
5 V
Core
This signal is fixed as input only and can be used
instead as PCI REQ[6:5]#.
95
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