Block Diagram - Measurement Computing PCI-CTR05 User Manual

PCI-CTR05 User's Guide

Block diagram

The block diagram shown here illustrates the functionality of the PCI-CTR05.
AMD9513 (equivalent)
16-bit counters
Input Clock0
Gate0
Counter 0
Output Clock0
Input Clock1
Gate1
Counter 1
Output Clock1
Input Clock2
Gate2 Counter 2
Output Clock2
Input Clock3
Counter 3
Gate3
Output Clock3
Input Clock4
Counter 4
Gate4
Output Clock4
Digital I/O
Output
Port
Input
Input (7:0)
Port
1.0/1.67/3.3/5.0 MHz
Controller FPGA and Logic
Control
Control
Bus
Registers
Decode/Status
Bus
Timing
Local Bus
PCI
Boot
Controller
EEPROM
PCI Bus (5V/3.3V, Universal 32-Bit, 33 MHz)
Figure 1-1. PCI-CTR05 functional block diagram
1-2
Introducing the PCI-CTR05
Clock Select
Clock
Divider
1.0/1.67/3.3/5.0 MHz
EXT_INT_EN
Int
Ctl
EXT_INT
Clock Select
BADR1
BADR2
Interrupt
10 MHz
Oscillator