Counter - Measurement Computing PCI-CTR05 User Manual

PCI-CTR05 User's Guide

Counter

Refer to the CTS9513-2 data sheet for complete 9513 specifications and operating modes. The SAVE
command for the CTS9513 device does not behave predictably when using clocks which are not
synchronous with the logic timing. The CTS9513-2 data sheet is available on our web site at
www.mccdaq.com/PDFmanuals/9513A.pdf.
Parameter
Counter type
Configuration
Compatibility
The 9513 device is programmable for:
Clock source
Gate:
Output:
Osc Out
Clock input frequency
X2 clock input sources
X2 clock frequency scaler
High pulse width (clock input)
Low pulse width (clock input)
Gate width high
Gate width low
Table 4-3. Counter specifications
Conditions
9513
One 9513 device. Five up/down counters, 16 bits each.
5V/TTL
Software selectable:
External:
Counter 1-5 clock inputs
Counter 1-5 gate inputs
Internal:
Terminal count of previous counter
X2 clock frequency scaler
Software selectable source:
External (default logic high):
Active high or low level or edge, counter 1 – 5 gate input
Active high level previous gate or next gate
All external gate signals (CTRxGATE) individually pulled up
through 10K resistors to +5V.
Internal:
Active high previous counter terminal count
No gating.
Software selectable:
Always low
High pulse on terminal count
Low pulse on terminal count
Toggle on terminal count
Inactive, high impedance at user connector counter # output.
Software selectable source:
Counter # input
Gate # input
Prescaled clock source (X2 clock frequency scaler)
Software selectable divider:
Division by 1-16
Software selectable enable:
On or low impedance to ground.
6.8 MHz max (145 nS min period)
Software selectable:
1.0 MHz (10 MHz Xtal divided by 10)
5.0 MHz (10 MHz Xtal divided by 2)
3.3 MHz (33 MHz PCI clock divided by 10)
1.67 MHz (33 MHz PCI clock divided by 20)
BCD scaling (X2 divided by 10, 100, 1000 or 10000) or Binary scaling
(X2 divided by 16, 256, 4096 or 65536)
70 ns min
70 ns min
145 ns min
145 ns min
4-2
Specifications