HP Visualize b1000 - Workstation Handbook page 82

Troubleshooting
Selftest Failures
Table 3-2. Chassis Codes for B1000/C3000 Workstations
Ostat Code FRU
FLT CBF2 SYS BD
FLT CBF3 SYS BD
FLT CBF4 SYS BD
FLT CBF5 SYS BD
WRN CBFA SYS BD
FLT CBFB SYS BD
FLT CBFC SYS BD
FLT CBFD SYS BD
FLT CBFE SYS BD
FLT CBFF SYS BD
INI CC0n SYS BD
INI CC1n SYS BD
INI CC2n SYS BD
INI CC3n SYS BD
82
Message
bad OS HPMC len
bad OS HPMC addr
bad OS HPMC cksm
OS HPMC vector 0
prev HPMC logged
brnch to OS HPMC
OS HPMC br err
unknown check
HPMC during TOC
multiple HPMCs
CPUn OS rendezvs
CPU n early rend
CPU n rendezvous
CPU n cache rend
Description
The size of the operating system HPMC
handler is invalid. Firmware will halt the
CPU, requiring a power cycle to recover.
The operating system HPMC handler
vector is invalid. Firmware will halt the
CPU, requiring a power cycle to recover.
The operating system HPMC handler
failed the checksum test. Firmware will
halt the CPU, requiring a power cycle to
recover.
The size of the operating system HPMC
handler is zero. Firmware will halt the
CPU, requiring a power cycle to recover.
Firmware detected unread PIM data from
a previous HPMC and will overwrite it.
Branching to the operating system HPMC
handler.
Branch to the operating system HPMC
handler failed. Firmware will halt the
CPU, requiring a power cycle to recover.
The firmware trap handler didn't detect
an HPMC, LPMC, or TOC.
A High-Priority Machine Check occurred
during Transfer of Control processing.
A High-Priority Machine Check occurred
while processing another HPMC.
Slave CPU n entering the final
rendezvous, waiting for the operating
system to awaken it.
Slave CPU n entering the early
rendezvous, waiting for the monarch CPU
to initialize scratch RAM and other
system state.
Slave CPU n entering rendezvous. Slave
CPUs enter this rendezvous numerous
times during boot.
Slave CPU n entering cached rendezvous,
waiting for the monarch CPU to configure
the system bus.
Chapter 3